Patent US5225357A successfully refreshed from Google Patents.
US5225357A
Expired / Lapsed
US
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Low P+ contact resistance formation by double implant
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1992-01-02
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Granted: 1993-07-06
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Expires: 2012-01-02
Abstract
Abstract The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less is done by providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric. Implanting of BF 2 + ions and B11+ ions sequentially by using the pattern as a mask. The structure is annealed at more than about 850° C. to complete the PMOS integrated circuit. This method results in lower contact resistance to the P+ regions and lower sheet resistance for higher speed CMOS integrated circuits at minimal increase of manufacturing cost.
Inventors
- 👤 Bernard W. K. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:31
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10P30/21; H10P30/212; H10P30/225; H10P30/28
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
71 words
The method of manufacture of a PMOS integrated circuit comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a heavily doped drain by (1) implanting BF 2 + ions using said pattern as a mask; (2) implanting B11+ ions using said pattern as a mask; and (c) annealing at between about 850° to 950° C. to form said PMOS integrated circuit.
Claim 2
Independent Claim
71 words
The method of manufacture of a PMOS integrated circuit comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a heavily doped drain by (1) implanting BF 2 + ions using said pattern as a mask; (2) implanting B11+ ions using said pattern as a mask; and (c) annealing at between about 850° to 950° C. to form said PMOS integrated circuit.
Claim 3
Dependent Claim
34 words
The method of claim 1 wherein energy of said BF 2 + ion implanting is between about 40 to 60 KEV and energy of said B11+ ion implanting is less than about 40 KEV.
Claim 4
Dependent Claim
48 words
The method of claim 1 wherein the dosage of said BF 2 + ion implanting is between about 1 to 2 E 15 atoms per cm 2 and the dosage of said B11+ ion implanting is between about 1 to 4 E 15 atoms per cm 2 .
Claim 5
Dependent Claim
29 words
The method of claim 1 wherein the total dosage of the two boron ion implanting species is between about 2 to 5 E 15 atoms per cm 2 .
Claim 6
Dependent Claim
34 words
The method of claim 1 and further comprising forming a sidewall insulator structure upon the sidewalls of said gate dielectric and gate electrodes pattern after ion implanting said BF 2 + into said substrate.
Claim 7
Dependent Claim
25 words
The method of claim 5 wherein said sidewall insulator is composed of silicon oxide and has a thickness of between about 1500 to 2500 Angstroms.
Claim 8
Independent Claim
76 words
The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a heavily doped drain region by sequentially implanting BF 2 + ions and B11+ ions using said pattern as a mask; and (c) annealing at more than about 850° C. to form said PMOS integrated circuit.
Claim 9
Independent Claim
76 words
The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a heavily doped drain region by sequentially implanting BF 2 + ions and B11+ ions using said pattern as a mask; and (c) annealing at more than about 850° C. to form said PMOS integrated circuit.
Claim 10
Dependent Claim
26 words
The method of claim 7 wherein said order of said sequentially implanting is to implant the BF 2 + ions first and the B11+ ions second.
Claim 11
Dependent Claim
26 words
The method of claim 7 wherein said order of said sequentially implanting is to implant the B11+ ions first and the BF 2 + ions second.
Claim 12
Dependent Claim
24 words
The method of claim 7 wherein said annealing is by furnace anneal between about 850° to 950° C. for more than about 30 minutes.
Claim 13
Dependent Claim
21 words
The method of claim 7 wherein said annealing is by rapid thermal anneal at a temperature more than about 1000° C.
Claim 14
Dependent Claim
34 words
The method of claim 7 wherein energy of said BF 2 + ion implanting is between about 40 to 60 KEV and energy of said B11+ ion implanting is less than about 40 KEV.
Claim 15
Dependent Claim
48 words
The method of claim 7 wherein the dosage of said BF 2 + ion implanting is between about 1 to 2 E 15 atoms per cm 2 and the dosage of said B11+ ion implanting is between about 1 to 4 E 15 atoms per cm 2 .
Claim 16
Dependent Claim
29 words
The method of claim 7 wherein the total dosage of the two boron ion implanting species is between about 2 to 5 E 15 atoms per cm 2 .
Claim 17
Dependent Claim
34 words
The method of claim 8 and further comprising forming a sidewall insulator structure upon the sidewalls of said gate dielectric and gate electrodes pattern after ion implanting said BF 2 + into said substrate.
Claim 18
Dependent Claim
25 words
The method of claim 15 wherein said sidewall insulator is composed of silicon oxide and has a thickness of between about 1500 to 2500 Angstroms.
Claim 19
Independent Claim
115 words
The method of manufacture of an lightly doped drain PMOS integrated circuit having a feature size in the order of one micron or less comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a lightly doped drain boron doped region in said substrate beneath and adjacent to said gate electrodes; (c) forming heavily doped drain regions by sequentially implanting BF 2 + ions and B11+ ions using said pattern as a mask which results in the total of said ions being the desired dopant for the heavily doped drain regions; and (d) annealing at more than about 850° C. to form said PMOS integrated circuit.
Claim 20
Independent Claim
115 words
The method of manufacture of an lightly doped drain PMOS integrated circuit having a feature size in the order of one micron or less comprising: (a) providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric; (b) forming a lightly doped drain boron doped region in said substrate beneath and adjacent to said gate electrodes; (c) forming heavily doped drain regions by sequentially implanting BF 2 + ions and B11+ ions using said pattern as a mask which results in the total of said ions being the desired dopant for the heavily doped drain regions; and (d) annealing at more than about 850° C. to form said PMOS integrated circuit.
Claim 21
Dependent Claim
34 words
The method of claim 17 wherein energy of said BF 2 + ion implanting is between about 40 to 60 KEV and energy of said B11+ ion implanting is less than about 40 KEV.
Claim 22
Dependent Claim
48 words
The method of claim 17 wherein the dosage of said BF 2 + ion implanting is between about 1 to 2 E 15 atoms per cm 2 and the dosage of said B11+ ion implanting is between about 1 to 4 E 15 atoms per cm 2 .
Claim 23
Dependent Claim
29 words
The method of claim 17 wherein the total dosage of the two boron ion implanting species is between about 2 to 5 E 15 atoms per cm 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |