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US5223736A Expired / Lapsed US ⏱️ 0.0 years remaining

Trench isolation process with reduced topography

Assignee: Texas Instruments Inc
•
Filing: 1991-05-22
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Granted: 1993-06-29
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Expires: 2011-05-22
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Abstract

Abstract A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Inventors

  • 👤 Mark S. Rodder

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:45
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 86 words
An isolation trench in an integrated circuit comprising: (a) a semiconductor body having a trench of a first depth; (b) a first dielectric layer on the vertical edges of said trench; (c) a plug within said trench, said plug filling said trench to a predetermined depth below the top of said trench; (d) a second dielectric layer on the vertical edges of and within said trench above said plug; and (e) a thermal oxide layer within said trench above said plug which substantially fills said trench.
Claim 2
Dependent Claim 86 words
An isolation trench in an integrated circuit comprising: (a) a semiconductor body having a trench of a first depth; (b) a first dielectric layer on the vertical edges of said trench; (c) a plug within said trench, said plug filling said trench to a predetermined depth below the top of said trench; (d) a second dielectric layer on the vertical edges of and within said trench above said plug; and (e) a thermal oxide layer within said trench above said plug which substantially fills said trench.
Claim 3
Dependent Claim 12 words
The isolation trench of claim 1, wherein said plug comprises polycrystalline silicon.
Claim 4
Dependent Claim 25 words
The isolation trench of claim 1, wherein said first dielectric layer comprises: (a) a layer of thermal oxide; and (b) a layer of TEOS oxide.
Claim 5
Dependent Claim 23 words
The isolation trench of claim 1 further comprising: (a) a doped region of said semiconductor body located at the bottom of said trench.
Claim 6
Dependent Claim 41 words
The isolation trench of claim 1, further comprising: (a) a well region of a second depth, said second depth less than said first depth, in said semiconductor body, said well region adjacent to a first and second side of said trench.
Claim 7
Dependent Claim 31 words
The isolation trench of claim 1, further comprising: (a) a field oxide region at a first portion of the surface of said semiconductor body, said field oxide region surrounding said trench.

References Cited (Backward Citations)

US4502913A Cited
US4495025A Cited
US4862240A Cited
US4983226A Cited
US4924284A Cited
US4903107A Cited
US4839306A Cited
US4825277A Cited
US5061653A Cited
US5017999A Cited
US4942137A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-06-28 1996-12-28 1997-06-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-06-28 2000-12-28 2001-06-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-06-28 2004-12-28 2005-06-29 $7700.00 Window Closed / Lapsed

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