Program control digital pulse generator

Claim 1

A pulse generating circuit comprising: counter means for counting a clock signal from an external circuit so as to be reset when the count value reaches a predetermined value; first register means for storing comparison value data to define a timing of a pulse generation; comparator means for detecting a coincidence between the count value of said counter means and the data of said register means to output a coincidence signal in response to the detection; second data register means for updating the contents of said first-data register means, said second data register means performing the updating operation in response to the coincidence signal from said comparator means; port latch means having a plurality of output terminals for generating output pulses in accordance with a designation made by an external circuit; data register means for storing data to designate the output terminal where the output pulse is to be generated and further for storing data to define an output state of the output terminal; and decoder means for decoding the contents of said data register means to output a decoded signal to said port latch means in synchronism with said coincidence signal outputted by said comparator means.