Architecture for data processor

Claim 1

A data processing system having an N-bit data bus, an M-bit data bus, and an M+N bit data address bus, and comprising: an instruction decoder for decoding instructions for the data processing system; an instruction register coupled to the instruction decoder for holding instructions to be decoded by the instruction decoder; an array of registers for storing variable data, the array of registers being coupled to the N-bit data bus; an arithmetic and logic unit coupled to the N-bit data bus and coupled to the instruction decoder, the arithmetic and logic unit being capable of performing operations on the data stored in the array of registers; a program counter for controlling sequence of instructions, the program counter being coupled to the address bus; a timer register capable of being incremented by one at a continuous rate, the timer register being coupled to the N-bit data bus; at least one capture register being capable of being loaded from the timer register, the at least one capture register being coupled to the N-bit data bus, to the timer register, and to an input terminal of the data processor system to allow the at least one capture register to be loaded from the timer register whenever a signal transition occurs on the input terminal; a compare register coupled to the N-bit data bus, the compare register being capable of being continuously compared for equality with the timer register to provide a signal when equality exists, the timer register thereby being capable of providing an output to the at least one capture register and of providing an output to be compared; and a command shift register coupled to the N-bit data bus and to an output terminal of the data processing system, the command shift register providing temporary storage of data and shifting the data out to the output terminal upon a predetermined command.