Digital signal processor

Claim 1

In a digital processor having: a control memory for storing a plurality of control instructions, each one having an address field and a control field; a program counter section for addressing such control memory in accordance with the contents stored in such control memory section; a control section for developing control signals in response to the control field of the addressed one of the control instructions and to condition signals; a data transfer bus; an arithmetic unit means responsive to the control signals for processing data applied to a pair of input terminals of such arithmetic unit means, such data being processed selectively in accordance with such control signals; means for coupling such processed data to the data transfer bus; and means coupled to the output of the arithmetic unit for producing the condition signals in accordance with the data processed by the arithmetic unit means, the improvement comprising: (a) a register means comprising: (i) a plurality of storage elements; (ii) input addressing means for enabling data on the data transfer bus to be stored into one of such storage elements selectively in accordance with the control signals; (iii) first output means for coupling data stored in any one of such storage elements to a first output terminal of such register means selectively in accordance with the control signals; and (iv) second output means for coupling data stored in any one of such storage elements to a second output terminal of such register means selectively in accordance with the control signal and wherein the first output terminal of the register means is coupled to one of the pair of input terminals of the arithmetic unit means; (b) means for coupling data on the first output terminal of the register means to the program counter section; (c) selector means having one input terminal connected to the program counter section and a second input terminal connected to the second output terminal of the register means for coupling either the program counter section or the second output terminal of the register means to the second one of the pair of input terminals of the arithmetic unit means selectively in accordance with the control signals; and (d) means, responsive to the control signals and the condition signals, for enabling the program counter section to store as the next address for the control memory either: (1) the prior contents stored in the program counter incremented or (2) an address comprising the address field of the currently addressed control instruction and the data on the first output terminal of the register means selectively in accordance with the condition signal.