Stored program computer with plural shift register storage

Claim 2

A stored program computer comprising a working memory including a plurality of short shift registers, each said short shift register having its output connected to its input to provide for normally recirculating its contents without change, a source of clock signals, a timing counter responding to said clock signals for defining successive character pair periods in said short shift registers, an instruction address register for storing the address of an instruction located in a specified one of the short shift registers and a specified character pair period therein, a flipflop for distinguishing an execute cycle and a non-execute cycle of the computer, each said cycle commensurate with a cycle of the short shift register, an instruction register in the form of a shift register having the capacity of a pair of characters, said instruction address register being effective during a nonexecute cycle of the computer to select a specified one of the short shift registers to shift its output through said instruction register, a comparator for comparing the successive character pair periods definged by said timing counter with the specified character pair period stored in said instruction address register and for terminating the shifting of the output of said selected short shift register through said instruction register when agreement is found leaving the specified instruction in said instruction register, said instruction address register providing for incrementing the specified character pair period stored therein after said comparison has been made, and a logic network, the instruction in said instruction register being effective during an execute cycle of the computer to render operable a portion of the logic network and to select a specified one of the short shift registers to suppress the recirculating of its contents without change and to alternately feed its output to and receive its input from said logic network whereby the content of said selected short shift register may be modified.

Claim 3

The invention in accordance with claim 1 including an accumulator register in the form of a short shift register having its output connected to its input for normally recirculating its contents without change in synchronism with the short shift registers of the working memory, said instruction in said instruction register being further effective during an execute cycle of the computer to render operable a portion of the logic network associated with the accumulator register to suppress the recirculating of its contents without change and to alternately feed its output to and receive its input from said logic network whereby the content of said accumulator register may be changed.

Claim 4

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for adding the contents of said selected short shift register into the accumulator register.

Claim 5

The invention in accordance with cLaim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for transferring the contents of the accumulator register into said selected short shift register.

Claim 6

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for transferring the contents of said selected short shift register into said accumulator register.

Claim 7

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for exchanging the contents of said selected short shift register with the contents of said accumulator register.

Claim 8

The invention in accordance with claim 1 which further comprises a bulk memory including a plurality of long shift registers, each said long shift register having its output connected to its input to provide for normally recirculating its content without change, each said long shift register having a capacity equal to a number of said short shift registers, and wherein the instruction in said instruction register is effective during a number of execute cycles of the computer to select a specified one of the long shift registers and to select a series of short shift registers and to render operable a portion of said logic network which provides for exchanging during each of said number of execute cycles the content of a selected different one of the series of short shift registers with the contents of a different portion of said selected one of said long shift registers.

Claim 9

The invention in accordance with claim 7 wherein said timing counter provides an output at the end of each character period, at the end of each character pair period, at the end of each short shift register cycle, and at the end of each long shift register cycle.

Claim 10

The invention in accordance with claim 2 including a bit manipulating flipflop coupled to said logic network, wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for utilizing the bit manipulating flipflop to manipulate the contents of a selected short shift register on a bit-by-bit basis.

Claim 11

The invention in accordance with claim 2 including a character manipulating group of flipflops coupled to said logic network, wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for utilizing the character manipulating flipflops to manipulate the contents of a selected short shift register on a character-by-character basis.

Claim 12

The invention in accordance with claim 2 including a bit manipulating flipflop coupled to said logic network, wherein the instruction in said instruction register is effective during the execute cycle of the computer to test the status of said bit manipulating flipflop and to provide for resetting the instruction address register so as to provide for obtaining the next instruction during the following non-execute cycle of the computer from the first character pair period of the selected register if said bit manipulating flipflop is in one state and to provide for obtaining the next instruction during the following non-execute cycle of the computer in accordance with the incremented present content of the instruction register if said bit manipulating flipflop is in the other state.

Claim 13

The invention in accordance with claim 2 including a character group of flipflips coupled to said logic network, and wherein the instruction in said instruction register is effective during each of a number of execute cycles of the computer to render operable a portion of said logic network which provides for repeatedly adding the contents of the selected short shift register into the accumulator register for a number of times determined by the character content of the character manipulating group of flipflops.

Claim 14

The invention in accordance with claim 2 wherein one of the characters of the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of the logic network which provides for clearing the accumulator register after a number of character periods as specified by the other of the characters of the instruction.

Claim 15

The invention in accordance with claim 2 wherein one of the characters of the instruction left in said instruction register is effective during the execute cycle of the computer to render operable a portion of the logic network which provides for processing the content of said accumulator register for a number of bit periods represented by the other character of said instruction.

Claim 16

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of the logical network which provides a signal on a selected outgoing line which is used to affect equipment external to the computer.

Claim 17

The invention in accordance with claim 2 including a bit manipulating flipflop coupled to said logic network, and wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of the logic network which provides for testing the logical level of an incoming line controlled by equipment external to the computer, said bit manipulating flipflop being triggered to a predetermined state if the signal on the incoming line is at a high logical level.

Claim 18

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for subtracting the contents of a selected short register from the accumulator register.

Claim 19

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for copying the last character of the selected short shift register by shifting it into the character manipulating group of flipflops.

Claim 20

The invention in accordance with claim 2 wherein the instruction in said instruction register is effective during the execute cycle of the computer to render operable a portion of said logic network which provides for decrementing the last character in the selected short shift register.

Claim 21

A stored program computer comprising a working memory including a plurality of short shift registers, each of said short shift registers having its output connected to its input to provide for normally recirculating its content without change, a bulk memory including a plurality of long shift registers, each of said long shift registers having its output connected to its input to provide for normally recirculating its content without change, each of said long shift registers having a capacity equal to a number of said short shift registers, and processing means including a logic network and an instruction register for operating on data stored in selected ones of said short shift registers of said working memory in accordance with a program of instructions stored in selected other ones of said short shift registers of said working memory, said program of instructions stored in said short shift registers including a memory exchange instruction which enables said processing means to render operable a portion of its logic network for successively connecting the output of each of a Number of short shift registers to the input of a selected long shift register and for connecting the output of the selected long shift register successively to the input of each of said number of short shift registers for exchanging the content of each of said number of short shift registers with the content of the selected one of said long shift registers, whereby said processing means is enabled to operate on data stored in selected ones of the short shift registers in accordance with the new program of instructions now stored in selected ones of the short shift registers.

Claim 22

A stored program computer comprising a working memory including a plurality of short shift registers, each of said short shift registers having its output connected to its input to provide for normally recirculating its content without change, a bulk memory including a plurality of long shift registers, each of said long shift registers having its output connected to its input to provide for normally recirculating its content without change, each of said long shift registers having a capacity equal to a number of said short shift registers, and processing means including a logic network and an instruction register for operating on data stored in selected ones of said short shift registers of said working memory in accordance with a program of instructions stored in selected other ones of said short shift registers of said working memory, said program of instructions stored in said short shift registers including a memory exchange instruction which enables said processing means to render operable a portion of its logic network for successively connecting the output of each of a Number of short shift registers to the input of a selected long shift register and for connecting the output of the selected long shift register successively to the input of each of said number of short shift registers for exchanging the content of each of said number of short shift registers with the content of the selected one of said long shift registers, whereby said processing means is enabled to operate on data stored in selected ones of the short shift registers in accordance with the new program of instructions now stored in selected ones of the short shift registers.

Claim 23

The invention in accordance with claim 10 wherein said computer includes a master reset switch which when manually operated provides for resetting to zero said short shift registers, said instruction address register, said instruction register, and said character group of flipflops, wherein said character group of flipflops is connected to successively receive characters from an outside source, and whereby the zero setting of said instruction register provides an initial fill instruction which is effective during each of a number of following execute cycles of the computer to select the short shift register identified by a zero address and to render operable a portion of said logic network which provides for transferring each of the characters received in said character group of flipflops into said selected short shift register.

Claim 24

In a data processing system: a working memory including a plurality of short shift registers, each said short shift registers having its output connected to its input to provide for normally recirculating its contents without change, a source of timing signals, a timing counter responding to said clock signals to define successive character pair periods of said short shift register, an output selector having a single output and a plurality of inputs, each associated with the output of a respective short shift register, an input selector having a single input and a plurality of outputs, each associated with the input of a respective short shift register, a logic network having an input connected to the single output of the output selector and having an output connected to the single input of the input selector, an instruction register including an address storage portion and an order storage portion, an instruction address register for storing the address of one of the short shift registers and the character pair period therein in which the next instruction to be performed is located, a control flipflop for distinguishing the execute and non-execute cycles of operation of the data processing system, said instruction address register operable during a cycle of operation to set the output selector in accordance with the address stored therein to enable the output of a selected one of the short shift registers to be connected to the single output of the output selector and shifted through the address portion and the order portion of said instruction register, comparing means for comparing the successive character pair periods of the timing counter with the character pair period of said instruction address register and for terminating said shifting when the instruction being sought is stored in said in-struction register, said address portion of the instruction register being effective when said control flipflop is in an execute cycle of operation to set the output selector and the input selector to suppress the recirculating of and to enable the output of a selected one of the short shift registers to be connected to the single output of the output selector and to enable the single input of said input selector to be connected to the input of the selected one of the short shift registers, and said order portion of said instruction register being effective when said control flipflop is in its execute cycle of operation for rendering a portion of said logic network operable, whereby The contents of the selected short shift register is modified in accordance with the portion of the logic network rendered operable.

Claim 25

In a data processing system: a working memory including a plurality of short shift registers, each said short shift registers having its output connected to its input to provide for normally recirculating its contents without change, a source of timing signals, a timing counter responding to said clock signals to define successive character pair periods of said short shift register, an output selector having a single output and a plurality of inputs, each associated with the output of a respective short shift register, an input selector having a single input and a plurality of outputs, each associated with the input of a respective short shift register, a logic network having an input connected to the single output of the output selector and having an output connected to the single input of the input selector, an instruction register including an address storage portion and an order storage portion, an instruction address register for storing the address of one of the short shift registers and the character pair period therein in which the next instruction to be performed is located, a control flipflop for distinguishing the execute and non-execute cycles of operation of the data processing system, said instruction address register operable during a cycle of operation to set the output selector in accordance with the address stored therein to enable the output of a selected one of the short shift registers to be connected to the single output of the output selector and shifted through the address portion and the order portion of said instruction register, comparing means for comparing the successive character pair periods of the timing counter with the character pair period of said instruction address register and for terminating said shifting when the instruction being sought is stored in said in-struction register, said address portion of the instruction register being effective when said control flipflop is in an execute cycle of operation to set the output selector and the input selector to suppress the recirculating of and to enable the output of a selected one of the short shift registers to be connected to the single output of the output selector and to enable the single input of said input selector to be connected to the input of the selected one of the short shift registers, and said order portion of said instruction register being effective when said control flipflop is in its execute cycle of operation for rendering a portion of said logic network operable, whereby The contents of the selected short shift register is modified in accordance with the portion of the logic network rendered operable.

Claim 26

In a data processing system a working memory including a plurality of short shift registers, each said short shift register having its output connected to its input to provide for normally recirculating its content without change; an output selector having a single output and a plurality of inputs, each associated with the output of a respective short shift register; an input selector having a single input and a plurality of outputs, each associated with the input of a respective short shift register; a logic network having an input connected to the single output of the output selector and having an output connected to the single input of the input selector; and an instruction register for storing an instruction including an address portion and an order portion; said address portion of said instruction register being effective to set said output selector and said input selector to suppress the recirculating of the contents of a selected one of the short shift registers without change by connecting the output of said selected one of the short shift registers to the single output of said output selector and by connecting the single input of said input selector to the input of said selected one of the short shift registers; and said order portion of said instruction register being effective to render a portion of said logic network operable; whereby said selected one of the short shift registers has its output connected to its input to provide for recirculating its contents as modified by said operable portion of said logic network.

Claim 27

In a data processing system a working memory including a plurality of short shift registers, each said short shift register having its output connected to its input to provide for normally recirculating its content without change; an output selector having a single output and a plurality of inputs, each associated with the output of a respective short shift register; an input selector having a single input and a plurality of outputs, each associated with the input of a respective short shift register; a logic network having an input connected to the single output of the output selector and having an output connected to the single input of the input selector; and an instruction register for storing an instruction including an address portion and an order portion; said address portion of said instruction register being effective to set said output selector and said input selector to suppress the recirculating of the contents of a selected one of the short shift registers without change by connecting the output of said selected one of the short shift registers to the single output of said output selector and by connecting the single input of said input selector to the input of said selected one of the short shift registers; and said order portion of said instruction register being effective to render a portion of said logic network operable; whereby said selected one of the short shift registers has its output connected to its input to provide for recirculating its contents as modified by said operable portion of said logic network.