Pulse generating circuit

Claim 2

A pulse generating circuit being provided with a counter which counts clock and is reset when said clock reaches a predetermined counting value, a register which alternately sets therein a first comparison value for defining the timing of the leading edge of an elementary pulse of a pulse signal to be outputted and a second comparison value for defining the timing of the trailing edge of the same, a digital comparator which compares the counting value of said counter with the comparison value of said register so as to output a coincidence signal when both said values are coincident with each other, and output level storage means which is previously set therein data signals corresponding to the level of a pulse signal to be outputted and which, when given a coincidence signal of said digital comparator, outputs said set data signals, comprises: a register buffer which stores therein said second comparison value to be set to said register, and, when given said coincidence signal from said digital comparator, sets said second comparison value at said register; and a control circuit which allows said register to store therein the first comparison value, said register buffer to store therein the second comparison value, and said output level storage means to store therein said data signal, with respect to each elementary pulse of the pulse signal to be outputted.

Claim 3

A pulse generating circuit as set forth in claim 1, wherein said output level storage means is a shift register in which the storage content is shifted in a looped manner.

Claim 4

A pulse generating circuit being provided with a counter which counts clock and is reset when said clock reaches a predetermined counting value, a register which alternately sets therein a first comparison value for defining the timing of the leading edge of an elementary pulse of a pulse signal to be outputted and a second comparison value for defining the timing of the trailing edge of the same, a digital comparator which compares the counting value of said counter with the comparison value of said register so as to output a coincidence signal when both said values are coincident with each other, and output level storage means which is previously set therein data signal corresponding to the level of a pulse signal to be outputted and which, when given a coincidence signal of said digital comparator, outputs said set data signals, comprises: a register buffer which stores therein said second comparison value to be set to said register, and when given said coincidence signal from said digital comparator, sets said second comparison value is set in said register; a counter buffer which stores therein a counting start value of said counter for defining each one cycle duration of the pulse signal to be outputted and sets the stored values at said counter when said counter reaches the predetermined value; and a control circuit which allows said register to store therein the first comparison value, said register buffer to store therein the second comparison value, said output level storage means to store therein said data signal, and said counter buffer to store the counting start value, with respect to each elementary pulse of said pulse signal to be outputted.

Claim 5

A pulse generating circuit being provided with a counter which counts clock and is reset when said clock reaches a predetermined counting value, a register which alternately sets therein a first comparison value for defining the timing of the leading edge of an elementary pulse of a pulse signal to be outputted and a second comparison value for defining the timing of the trailing edge of the same, a digital comparator which compares the counting value of said counter with the comparison value of said register so as to output a coincidence signal when both said values are coincident with each other, and output level storage means which is previously set therein data signal corresponding to the level of a pulse signal to be outputted and which, when given a coincidence signal of said digital comparator, outputs said set data signals, comprises: a register buffer which stores therein said second comparison value to be set to said register, and when given said coincidence signal from said digital comparator, sets said second comparison value is set in said register; a counter buffer which stores therein a counting start value of said counter for defining each one cycle duration of the pulse signal to be outputted and sets the stored values at said counter when said counter reaches the predetermined value; and a control circuit which allows said register to store therein the first comparison value, said register buffer to store therein the second comparison value, said output level storage means to store therein said data signal, and said counter buffer to store the counting start value, with respect to each elementary pulse of said pulse signal to be outputted.

Claim 6

A pulse generating circuit as set forth in claim 3, wherein said output level storage means is a shift register in which the stored content is shifted in a looped manner.