US5216423A
Expired / Lapsed
US
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Method and apparatus for multiple bit encoding and decoding of data through use of tree-based codes
Assignee: University of Central Florida
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Filing: 1991-04-09
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Granted: 1993-06-01
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Expires: 2011-04-09
Abstract
Abstract A decoder/encoder apparatus is provided which can be programmed to decode data and to encode data. To encode data, a memory within the apparatus is preloaded with a first memory map which is descriptive of a selected tree-based binary code. The first memory map is a reverse tree representation of the selected tree-based binary code. Data is then provided to the apparatus and is processed as specified by the first memory map thus generating encoded data. To decode data, the same memory is preloaded with a second memory map which is descriptive of the same selected tree-based binary code. The second memory map is a tree representation of the same selected tree-based binary code. Encoded data is then provided to the apparatus and is processed as specified by the second memory map thus generating decoded data.
Inventors
- 👤 Amae Mukherjee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:15
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/40; H03M7/42
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
102 words
A method for encoding data in an encoder, said encoder including a memory having a plurality of memory locations containing data for simultaneous generation of multiple bits of tree-based binary codes in a single memory access cycle, said method comprising the steps of: preloading said memory with a memory map descriptive of a selected multiple bit tree-based binary code, said memory map being a reverse tree representation of said selected multiple bit tree-based binary code; providing data to said encoder; and encoding multiple bits of said data in each memory access cycle as specified by said memory map to generate encoded data.
Claim 2
Independent Claim
102 words
A method for encoding data in an encoder, said encoder including a memory having a plurality of memory locations containing data for simultaneous generation of multiple bits of tree-based binary codes in a single memory access cycle, said method comprising the steps of: preloading said memory with a memory map descriptive of a selected multiple bit tree-based binary code, said memory map being a reverse tree representation of said selected multiple bit tree-based binary code; providing data to said encoder; and encoding multiple bits of said data in each memory access cycle as specified by said memory map to generate encoded data.
Claim 3
Dependent Claim
55 words
The method of claim 1 wherein said preloading step comprises loading an encoding tree into said memory, said encoding tree being a multiple bit reverse binary tree including a root node and a plurality of leaf nodes, said leaf nodes being mapped into said memory locations within said memory in one to one correspondence therewith.
Claim 4
Independent Claim
90 words
A method for decoding data in an decoder, said decoder including a memory having a plurality of memory locations, each memory location containing data for simultaneous decoding of multiple bits of a tree-based binary code in a single memory access cycle, said method comprising the steps of: preloading said memory with a memory map descriptive of a selected multiple bit tree-based binary code; providing data to said decoder; and decoding multiple bits of said data in each memory access cycle as specified by said memory map to generate decoded data.
Claim 5
Independent Claim
90 words
A method for decoding data in an decoder, said decoder including a memory having a plurality of memory locations, each memory location containing data for simultaneous decoding of multiple bits of a tree-based binary code in a single memory access cycle, said method comprising the steps of: preloading said memory with a memory map descriptive of a selected multiple bit tree-based binary code; providing data to said decoder; and decoding multiple bits of said data in each memory access cycle as specified by said memory map to generate decoded data.
Claim 6
Dependent Claim
51 words
The method of claim 3 wherein said preloading step comprises loading a multiple bit binary decoding tree into said memory, said decoding tree including a root node and a plurality of leaf nodes, said leaf nodes being mapped into said memory locations within said memory in one to one correspondence therewith.
Claim 7
Independent Claim
120 words
A method for decoding and encoding data in an decoder/encoder, said decoder/encoder including a memory, said method comprising the steps of: preloading said memory with a first memory map descriptive of a selected tree-based binary code, said first memory map being a multiple bit reverse tree representation of said selected tree-based binary code; preloading said memory with a second memory map descriptive of said selected multiple bit binary tree-based binary code, said second memory map being a tree representation of said selected tree-based binary code; providing first data to said decoder/encoder; encoding said first data as specified by said first memory map; providing second data to said decoder/encoder; and decoding said second data as specified by said second memory map.
Claim 8
Independent Claim
120 words
A method for decoding and encoding data in an decoder/encoder, said decoder/encoder including a memory, said method comprising the steps of: preloading said memory with a first memory map descriptive of a selected tree-based binary code, said first memory map being a multiple bit reverse tree representation of said selected tree-based binary code; preloading said memory with a second memory map descriptive of said selected multiple bit binary tree-based binary code, said second memory map being a tree representation of said selected tree-based binary code; providing first data to said decoder/encoder; encoding said first data as specified by said first memory map; providing second data to said decoder/encoder; and decoding said second data as specified by said second memory map.
Claim 9
Dependent Claim
80 words
An encoder apparatus for encoding data comprising: means for receiving data to be encoded; a memory including a plurality of memory locations; preloading means, coupled to said memory, for preloading said memory with a memory map descriptive of a selected tree-based binary code, said memory map being a multiple bit reverse tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said data as specified by said memory map to encode said data.
Claim 10
Dependent Claim
80 words
An encoder apparatus for encoding data comprising: means for receiving data to be encoded; a memory including a plurality of memory locations; preloading means, coupled to said memory, for preloading said memory with a memory map descriptive of a selected tree-based binary code, said memory map being a multiple bit reverse tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said data as specified by said memory map to encode said data.
Claim 11
Dependent Claim
68 words
The encoder apparatus of claim 6 wherein said preloading means further includes means for loading an encoding tree into said memory, said encoding tree being a multiple bit reverse tree including a root node and a plurality of internal and leaf nodes, at least some of said internal nodes and said leaf nodes being mapped into said memory locations within said memory in one to one correspondence therewith.
Claim 12
Dependent Claim
79 words
An decoder apparatus for decoding data comprising: means for receiving data to be decoded; a memory including a plurality of memory locations; preloading means, coupled to said memory, for preloading said memory with a memory map descriptive of a selected tree-based binary code, said memory map being a multiple bit tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said data as specified by said memory map to decode said data.
Claim 13
Dependent Claim
79 words
An decoder apparatus for decoding data comprising: means for receiving data to be decoded; a memory including a plurality of memory locations; preloading means, coupled to said memory, for preloading said memory with a memory map descriptive of a selected tree-based binary code, said memory map being a multiple bit tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said data as specified by said memory map to decode said data.
Claim 14
Dependent Claim
51 words
The apparatus of claim 8 wherein said preloading means further includes means for loading a decoding tree into said memory, said decoding tree including a root node and a plurality of leaf nodes, said leaf nodes being mapped into said memory locations within said memory in one to one correspondence therewith.
Claim 15
Dependent Claim
150 words
A decoder/encoder apparatus for decoding and encoding data comprising: first receiving means for receiving first data to be encoded; second receiving means for receiving second data to be decoded; a memory; first preloading means, coupled to said memory, for loading said memory with a first memory map descriptive of a selected tree-based binary code, said first memory map being a multiple bit reverse tree representation of said selected tree-based binary code; second preloading means, coupled to said memory, for loading said memory with a second memory map descriptive of said selected tree-based binary code, said second memory map being a multiple bit tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said first data as specified by said first memory map to encode said data and for processing said second data as specified by said second memory map to decode the data.
Claim 16
Dependent Claim
150 words
A decoder/encoder apparatus for decoding and encoding data comprising: first receiving means for receiving first data to be encoded; second receiving means for receiving second data to be decoded; a memory; first preloading means, coupled to said memory, for loading said memory with a first memory map descriptive of a selected tree-based binary code, said first memory map being a multiple bit reverse tree representation of said selected tree-based binary code; second preloading means, coupled to said memory, for loading said memory with a second memory map descriptive of said selected tree-based binary code, said second memory map being a multiple bit tree representation of said selected tree-based binary code; and processing means, coupled to said memory, for processing said first data as specified by said first memory map to encode said data and for processing said second data as specified by said second memory map to decode the data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |