Run length code decoder

Claim 2

A binary code decoder comprising: memory means for containing a decode table for decoding a binary code consisting of a plurality of binary signals; count means for counting one kind of the binary signals; determining means for determining an address of said memory means to be first accessed in accordance with a count of said count means and for determining a decode address of the binary code in accordance with data recorded at the first accessed address of said memory means and remaining portions of the binary code not counted by said count means; and reading means for reading data recorded at the decode address determined by said determining means.

Claim 3

A binary code decoder according to claim 1 wherein the binary code is a variable-length code.

Claim 4

A binary code decoder according to claim 1 wherein said count means counts "0" signals successively from the beginning of the binary code.

Claim 5

A binary code decoder according to claim 1 wherein data recorded in said memory means is provided with a code indicating whether or not the recorded data is decode data.

Claim 6

A binary code decoder according to claim 1 wherein said determining means decides whether data read by said reading means is decode data and, when the data is not decode data, said determining means determines the next address.

Claim 7

A binary code decoder according to claim 1 wherein said determining means decides whether data read by said reading means is decode data and, when the data is not decode data, said determining means determines the next address by adding the data to the remaining portions of the binary code.

Claim 8

A binary code decoder according to claim 1 wherein the binary code is a run length code.

Claim 9

A run length code decoder comprising: memory means containing a decode table for a run length code represented by a code tree; count means for counting the number of predetermined bits included in an input code consisting of a combination of "0's" and "1's", wherein said predetermined bits counted by said count means are leading "0's" in said input code; means for determining an address of said memory means to be first accessed in accordance with a count of said count means; and means for sequentially and selectively accessing addresses of said memory means to produce a decoded signal of said run length code.

Claim 10

A run length code decoder comprising: memory means containing a decode table for a run length code represented by a code tree; count means for counting the number of predetermined bits included in an input code consisting of a combination of "0's" and "1's", wherein said predetermined bits counted by said count means are leading "0's" in said input code; means for determining an address of said memory means to be first accessed in accordance with a count of said count means; and means for sequentially and selectively accessing addresses of said memory means to produce a decoded signal of said run length code.

Claim 11

A run length code decoder comprising: detection means for detecting one input code; count means for counting the number of other input codes; arithmetic operation means for receiving a detection signal from said detection means and a count from said count means and arithmetically operating said count and a predetermined initial value; memory means containing a decode table for a run length code represented by a code tree, an address of said memory means to be first accessed being determined by an output of said arithmetic operation means; and means for outputting a signal decoded by said memory means.

Claim 12

A run length code decoder comprising: detection means for detecting one input code; count means for counting the number of other input codes; arithmetic operation means for receiving a detection signal from said detection means and a count from said count means and arithmetically operating said count and a predetermined initial value; memory means containing a decode table for a run length code represented by a code tree, an address of said memory means to be first accessed being determined by an output of said arithmetic operation means; and means for outputting a signal decoded by said memory means.

Claim 13

A run length code decoder according to claim 9 wherein said detection means detects an input "1" signal and said count means counts the number of input "0" signals.

Claim 14

A run length code decoder comprising: memory means containing a decode table for a run length code represented by a code tree, said memory means determining an address in accordance with an input signal; arithmetic operation means for arithmetically operating a predetermined address set to said memory means, a content at said predetermined address and the next data derived from the input code to determine an address of said memory means to be next read; end detection means for detecting an end of decoding operation based on a signal produced by said memory means; and means for outputting a signal decoded by said memory means in response to a detection signal from said end detection means.

Claim 15

A run length code decoder comprising: memory means containing a decode table for a run length code represented by a code tree, said memory means determining an address in accordance with an input signal; arithmetic operation means for arithmetically operating a predetermined address set to said memory means, a content at said predetermined address and the next data derived from the input code to determine an address of said memory means to be next read; end detection means for detecting an end of decoding operation based on a signal produced by said memory means; and means for outputting a signal decoded by said memory means in response to a detection signal from said end detection means.

Claim 16

A run length code detector comprising: detection means for detecting one input code; count means for counting the number of other input codes; memory means containing a decode table for a run length code represented by a code tree, an address of said memory means to be first accessed being determined by a count of said count means; first arithmetic operation means for receiving a detection signal from said detection means, outputting the count of said count means to said memory means and arithmetically operating a next data derived from the input code and other input signal; second arithmetic operation means for supplying a result of an arithmetic operation of a predetermined address from said first arithmetic operation means and a content at the predetermined address of said memory means, or a predetermined initial value to said memory means and supplying said other input signal to said first arithmetic operation means; end detection means for detecting an end of decoding operation by a signal outputted from said memory means; and means for outputting a signal decoded by said memory means in response to a detection signal from said end detection means.

Claim 17

A run length code detector comprising: detection means for detecting one input code; count means for counting the number of other input codes; memory means containing a decode table for a run length code represented by a code tree, an address of said memory means to be first accessed being determined by a count of said count means; first arithmetic operation means for receiving a detection signal from said detection means, outputting the count of said count means to said memory means and arithmetically operating a next data derived from the input code and other input signal; second arithmetic operation means for supplying a result of an arithmetic operation of a predetermined address from said first arithmetic operation means and a content at the predetermined address of said memory means, or a predetermined initial value to said memory means and supplying said other input signal to said first arithmetic operation means; end detection means for detecting an end of decoding operation by a signal outputted from said memory means; and means for outputting a signal decoded by said memory means in response to a detection signal from said end detection means.

Claim 18

A run length code decoder according to claim 12 wherein said detection means detects an input "1" signal and said count means counts the number of input "0" signals.

Claim 19

A run length code decoder according to claim 12 wherein when said first arithmetic operation means receives the count from said count means and the predetermined initial value from said second arithmetic operation means, the address of said memory means to be first accessed is determined by the output of said first arithmetic operation means.

Claim 20

A run length code decoder according to claim 12 wherein when said first arithmetic operation means receives the next data derived from the input code and the operation result from said second arithmetic operation means, the address of said memory means to be next read is determined by the output of said first arithmetic operation means.

Claim 21

A run length code decoder according to claim 12 wherein said first arithmetic operation means and said second arithmetic operation means are adders for adding input signals thereto.

Claim 22

A run length code decoder according to claim 13, wherein when said first arithmetic operation means receives the count from said count means and the predetermined initial value from said second arithmetic operation means, the address of said memory means to be first accessed is determined by the output of said first arithmetic operation means.

Claim 23

A run length code decoder according to claim 13, wherein when said first arithmetic operation means receives the next data derived from the input code and the operation result from said second arithmetic operation means, the address of said memory means to be next read is determined by the output of said first arithmetic operation means.

Claim 24

A run length code decoder according to claim 13, wherein said first arithmetic operation means and said second arithmetic operation means are adders for adding input signals thereto.