Decoding apparatus for codes represented by code tree

Claim 3

A decoding apparatus according to claim 1 wherein the information indicating the number of bits to be entered is a variable number not exceeding the number of branches from a root or internal node to the nearest terminal node in the code tree.

Claim 4

A decoding apparatus according to claim 1 or 2 comprising an initial data memory for storing therein the number of bits to be entered first for each code of the input code train.

Claim 5

A decoding apparatus for decoding variable length codes represented by a code tree comprising: data input means for receiving an input code train; a decoding table memory having address locations each for storing terminal data including a bit area indicating completion of decoding, a bit area indicating decoded result information, and a bit area indicating the number of bits to be entered first for each code, said decoding table memory also having address locations each for storing intermediate data including a bit area indicating incompletion of decoding and a bit area indicating address information for determining an address of said decoding table memory to be accessed; readout means for accessing said decoding table memory to read out data therefrom; means for detecting the information in said read out data which indicates completion or incompletion of decoding, said detecting means being operative to determine whether the read out data is terminal data or intermediate data; output means for receiving the decoded result information read out from said decoding table memory and for outputting decoded data when the read out data from said decoding table memory is determined by said detecting means to be terminal data; input control means for controlling the number of bits to be entered by said data input means for the input code train; a fixed data memory for supplying a predetermined fixed number m (m being an interger of at least 2) indicating the number of bits to be entered by said data input means to said input control means when the read out data is determined by said detecting means to be intermediate data; address operating means, responsive to a determination by said detecting means that the read out data is intermediate data, for processing the information of the intermediate data and the data entered by said data input means to produce an address of said decoding table memory to be accessed next; selector means, responsive to a determination by said detecting means that the read out data is terminal data, for supplying the data in the bit area indicating the decoded result information to said output means, said selector means being responsive to a determination by said detecting means that the read out data is intermediate data for supplying the data in the bit area indicating address information to said address operating means; and data setting means, responsive to a determination by said detecting means that the read out data is terminal data, for receiving data in the read out data which indicates the number of bits to be entered first and for setting said number into said input control means.

Claim 6

A decoding apparatus for decoding variable length codes represented by a code tree comprising: data input means for receiving an input code train; a decoding table memory having address locations each for storing terminal data including a bit area indicating completion of decoding, a bit area indicating decoded result information, and a bit area indicating the number of bits to be entered first for each code, said decoding table memory also having address locations each for storing intermediate data including a bit area indicating incompletion of decoding and a bit area indicating address information for determining an address of said decoding table memory to be accessed; readout means for accessing said decoding table memory to read out data therefrom; means for detecting the information in said read out data which indicates completion or incompletion of decoding, said detecting means being operative to determine whether the read out data is terminal data or intermediate data; output means for receiving the decoded result information read out from said decoding table memory and for outputting decoded data when the read out data from said decoding table memory is determined by said detecting means to be terminal data; input control means for controlling the number of bits to be entered by said data input means for the input code train; a fixed data memory for supplying a predetermined fixed number m (m being an interger of at least 2) indicating the number of bits to be entered by said data input means to said input control means when the read out data is determined by said detecting means to be intermediate data; address operating means, responsive to a determination by said detecting means that the read out data is intermediate data, for processing the information of the intermediate data and the data entered by said data input means to produce an address of said decoding table memory to be accessed next; selector means, responsive to a determination by said detecting means that the read out data is terminal data, for supplying the data in the bit area indicating the decoded result information to said output means, said selector means being responsive to a determination by said detecting means that the read out data is intermediate data for supplying the data in the bit area indicating address information to said address operating means; and data setting means, responsive to a determination by said detecting means that the read out data is terminal data, for receiving data in the read out data which indicates the number of bits to be entered first and for setting said number into said input control means.

Claim 7

A decoding apparatus according to claim 1 or 4 wherein each of said address locations for storing terminal data includes a bit area indicating whether the decoded data is a terminating code or a make up code.

Claim 8

A decoding apparatus according to claim 5 wherein said output means comprises an output latch having a number of output terminals which are twice the number of bits in the bit area indicating the decoded result information, said output terminals respectively corresponding to binary weighted output bits, and changeover means for receiving the decoded result information from said decoding table memory through said selector means and for supplying the decoded result information to the output terminals corresponding to the lower order half of the output bits when the read out data is determined to be terminal data and the decoded data is a terminating code, and for supplying the decoded result information to the output terminals corresponding to the higher order half of the output bits when the read out data is determined to be terminal data and the decoded data is a make up code.

Claim 9

A decoding apparatus according to claim 1 or 4 wherein said bit area indicating the completion of decoding in the terminal data and said bit area indicating incompletion of decoding in the intermediate data are at the same bit location.

Claim 10

A decoding apparatus according to claim 1 or 4 wherein said bit area indicating decoded result information in the terminal data and said bit area indicating address information in the terminal data are at the same bit locations.

Claim 11

A decoding apparatus according to claim 4 wherein the information indicating the number of bits to be entered first is L-(n-1)m, where L is the code length decoded at that time and n is the number of accesses made to the decoding table memory for the decoding.

Claim 12

A decoding apparatus according to claim 1 or 4 wherein the terminal data includes information indicating the kind of a decoded code.

Claim 13

A decoding apparatus according to claim 1 or 4 wherein the address operating means is means for performing an add operation.