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US5214770A
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System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-06-21
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Granted: 1993-05-25
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Expires: 2010-06-21
Abstract
Abstract A method and apparatus for optimizing the performance of a multiple cache system computer having separate caches for data and instructions in which all writes to the data cache are monitored. If the address tag of the item being written matches one of a list of tags representing valid instructions currently stored in the instruction cache, a flag called I -- FLUSH -- ON -- REI is set. Until this flag is set, REI (Return from Exception or Interrupt) instructions will not flush the instruction cache. When the flag is set, an REI command will also flush or clear the instruction cache. Thus, the instruction cache is only flushed when an address referenced by an instruction is modified, so as to reduce the number of times the cache is flushed and optimize the computer's speed of operation.
Inventors
- 👤 Raj K. Ramanujan
- 👤 Peter J. Bannon
- 👤 Simon C. Steely, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F9/3861
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
131 words
A method for synchronizing data and instructions in a computer having a translation buffer, an instruction cache arranged to store blocks of information, a data cache, a tag store, and a Return from Exception or Interrupt command, the method comprising the steps of: storing, in the tag store, first addresses corresponding to the blocks of information contained in the instruction cache; utilizing a comparator to compare said stored first addresses with second addresses of data being written to said data cache by the computer; setting an indicator bit if a match of any of said first addresses with any of said second addresses is detected in said comparing step; and clearing said instruction cache when said indicator bit is set and upon execution of said Return from Exception or Interrupt command.
Claim 2
Independent Claim
131 words
A method for synchronizing data and instructions in a computer having a translation buffer, an instruction cache arranged to store blocks of information, a data cache, a tag store, and a Return from Exception or Interrupt command, the method comprising the steps of: storing, in the tag store, first addresses corresponding to the blocks of information contained in the instruction cache; utilizing a comparator to compare said stored first addresses with second addresses of data being written to said data cache by the computer; setting an indicator bit if a match of any of said first addresses with any of said second addresses is detected in said comparing step; and clearing said instruction cache when said indicator bit is set and upon execution of said Return from Exception or Interrupt command.
Claim 3
Dependent Claim
63 words
A method of claim 1, wherein the indicator bit comprises a flag for each said block contained in the instruction cache, said flag being set to indicate said match of said first and second addresses for a corresponding block in the instruction cache, and wherein the step of clearing said instruction cache includes clearing selected individual blocks having a flag that is set.
Claim 4
Independent Claim
160 words
An apparatus for insuring synchronism between an instruction cache and a data cache of a computer, the apparatus comprising: means for storing first addresses referred to by said instruction cache; means for comparing addresses in the means for storing first addresses, said means for comparing addresses operated to compare said first address with second addresses of data being written to said data cache by the computer; means for setting and storing, coupled to said means for comparing addresses, operating to set and store a flag bit when a match between any one of said first addresses and any one of said second addresses occurs; and means responsive to a Return from Exception or Interrupt command coupled to said instruction cache and said means for setting and storing, said means responsive to a Return from Exception or Interrupt command operating to clear the instruction cache in response to the Return from Exception or Interrupt command when the flag bit is set.
Claim 5
Independent Claim
160 words
An apparatus for insuring synchronism between an instruction cache and a data cache of a computer, the apparatus comprising: means for storing first addresses referred to by said instruction cache; means for comparing addresses in the means for storing first addresses, said means for comparing addresses operated to compare said first address with second addresses of data being written to said data cache by the computer; means for setting and storing, coupled to said means for comparing addresses, operating to set and store a flag bit when a match between any one of said first addresses and any one of said second addresses occurs; and means responsive to a Return from Exception or Interrupt command coupled to said instruction cache and said means for setting and storing, said means responsive to a Return from Exception or Interrupt command operating to clear the instruction cache in response to the Return from Exception or Interrupt command when the flag bit is set.
Claim 6
Dependent Claim
87 words
The apparatus of claim 3, wherein: said means for setting and storing, operating to set and store a flag indicative of a match of at least one of said first addresses with at least one of said second addresses in said means for comparing addresses; and said means responsive to a Return from Exception of Interrupt command operating to clear the instruction cache by clearing that portion of said instruction cache containing data corresponding to the at least one of said first addresses identified as a match.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |