Patent US5214654A successfully refreshed from Google Patents.
US5214654A
Expired / Lapsed
US
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Memory tester
Assignee: Advantest Corp
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Filing: 1991-01-03
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Granted: 1993-05-25
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Expires: 2011-01-03
Abstract
Abstract In a memory tester for testing memories of the type having a polarity inversion feature there are provided a bit select circuit for selecting from an address generated by an address generator a plurality of bits necessary for a logical expression expressing a polarity-inverted data storage area of the memory under test and a bit register circuit for storing bit data which is used to supply the bit select circuit with a select signal for specifying bits to be selectively output. The bits selectively output by the bit select circuit are used as an address for reading out a polarity inversion control signal from an area inversion memory. A polarity inverter, supplied with test data signal from a data generator, outputs the test data intact or after inverting its polarity in accordance with the logic of the polarity inversion control signal, and the output data is written into the memory under test.
Inventors
- 👤 Toshimi Oosawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
249 words
A memory tester for testing memories equipped with a polarity inversion feature, comprising: a memory under test; an address generating section, operatively connected to said memory under test, for generating an address signal to be applied to said memory under test; a data generating section, operatively connected to said memory under test, for generating a test data signal to be applied to said memory under test in synchronism with said address signal from said address generating section and for generating an expected value data; a polarity inverter, operatively connected to said data generating section, responsive to a polarity inversion signal to invert the polarity of said test data signal to be applied from said data generating section to said memory under test; and a polarity controller, operatively connected to said polarity inverter, for applying said polarity inversion signal to said polarity inverter, said polarity controller including: a bit register circuit which stores bit data for specifying in said address signal a plurality of bits necessary for a logical expression which expresses a polarity-inverted data storage area and outputs a bit data set; a bit select circuit for selectively outputting those bits in said address signal specified by said bit data set in said bit register circuit; and an area inversion memory which is accessed by a composite address signal composed of said plurality of bits selectively output by said bit select circuit to read out said polarity inversion signal, said polarity inversion signal being applied to said polarity inverter.
Claim 2
Dependent Claim
249 words
A memory tester for testing memories equipped with a polarity inversion feature, comprising: a memory under test; an address generating section, operatively connected to said memory under test, for generating an address signal to be applied to said memory under test; a data generating section, operatively connected to said memory under test, for generating a test data signal to be applied to said memory under test in synchronism with said address signal from said address generating section and for generating an expected value data; a polarity inverter, operatively connected to said data generating section, responsive to a polarity inversion signal to invert the polarity of said test data signal to be applied from said data generating section to said memory under test; and a polarity controller, operatively connected to said polarity inverter, for applying said polarity inversion signal to said polarity inverter, said polarity controller including: a bit register circuit which stores bit data for specifying in said address signal a plurality of bits necessary for a logical expression which expresses a polarity-inverted data storage area and outputs a bit data set; a bit select circuit for selectively outputting those bits in said address signal specified by said bit data set in said bit register circuit; and an area inversion memory which is accessed by a composite address signal composed of said plurality of bits selectively output by said bit select circuit to read out said polarity inversion signal, said polarity inversion signal being applied to said polarity inverter.
Claim 3
Dependent Claim
37 words
The memory tester of claim 1, wherein said bit select circuit includes a predetermined number of multiplexers each of which is supplied with said address signal and selectively outputs a specified one bit in said address signal.
Claim 4
Dependent Claim
29 words
The memory tester of claim 1, wherein said area inversion memory has stored therein one logic of said polarity inversion signal at every address which satisfies said logical expression.
Claim 5
Dependent Claim
77 words
The memory tester of claim 1, further comprising: another polarity inverter which is supplied with said expected value data signal and outputs said expected value data signal intact or after converting its logic in accordance with a logic of said polarity inversion signal; and a logic comparator for making a logical comparison between the output of said another polarity inverter and data read out of said memory under test and outputting a result of said logical comparison.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |