Abstract A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V pp supply voltage source which is in excess of high logic level voltage V dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V pp supply voltage level directly to the word line through the source-drain circuit of an FET. Thus an above V dd voltage level on the word line is achieved without the use of double boot-strap circuits.
A dynamic random access memory (DRAM) comprising bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V pp supply voltage source which is in excess of high logic level voltage V dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V pp supply voltage level directly to the word line through the source-drain circuit of an FET.
Claim 2
Dependent Claim
134 words
A dynamic random access memory (DRAM) comprising bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V pp supply voltage source which is in excess of high logic level voltage V dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V pp supply voltage level directly to the word line through the source-drain circuit of an FET.
Claim 3
Dependent Claim
50 words
A DRAM as defined in claim 1 in which said selecting means is comprised of means for receiving V dd level logic inputs and for providing an output to said applying means at V pp logic levels, the level V pp being higher than the supply voltage V dd .
Claim 4
Dependent Claim
76 words
A DRAM as defined in claim 2 in which the applying means is comprised of a level shifter connected to said high supply voltage source having an output connected to the gate of a pass transistor whose source is connected to said high supply voltage source, said word line and level shifter driving means being connected between the level shifter and ground, the level shifter driving means being connected to the output of the selecting means.
Claim 5
Dependent Claim
148 words
A DRAM as defined in claim 3 in which the level shifter is comprised of a pair of cross coupled P-channel FETs, the level shifter having a pair of control nodes and a power supply node, the power supply node being connected to said high supply voltage source, one of the control nodes forming said output, the level shifter driving means being comprised of an input connected to the output of the selecting means, an inverter having an input connected to said output of the selecting means, a pair of N-channel FETs each having source-drain circuits connected between a corresponding one of said control nodes and ground, the gate of one of said N-channel FETs which is connected to said one control node being connected to the output of said inverter, and the gate of the other N-channel FET being connected to said output of the selecting means.
Claim 6
Dependent Claim
18 words
A DRAM as defined in claim 1 in which said selecting means is comprised of a NAND gate.