Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors

Claim 2

A decoder circuit, used in a programmable read only memory, comprising: a first high potential power supply line for supplying a voltage changeable between a high voltage and a low voltage; a low potential power supply line; a load means connected between said first high potential power supply line and a decoded output terminal; a plurality of decoder transistors, connected in series between said decoded output terminal and said low potential power supply line, and gates of said decoder transistors being supplied with input signals; a current supply means, connected to at least one of a plurality of connection points of said decoder transistors, for supplying a current to said at least one of said connection points, when at least one of said decoder transistors except the nearest decoder transistor of said decoded output terminal is switched OFF.

Claim 3

A decoder circuit, as claimed in claim 1, wherein said current supply means is connected to one point of said plurality of connection points.

Claim 4

A decoder circuit, as claimed in claim 2, wherein said current supply means is connected to the nearest connection point of said decoded output terminal in said connection points.

Claim 5

A decoder circuit, as claimed in claim 1, wherein said decoder transistors are formed by first conduction type MOS transistors; and said current supply means comprises a plurality of current supply transistors formed by second conduction type MOS transistors opposite to said first conduction type, sources of said current supply transistors are connected to a second high potential power supply line for supplying said low voltage, drains of said current supply transistors are connected to said at least one of said connection points, and gates of said current supply transistors are supplied with the input signals except the nearest input signal received by the nearest decoder transistor of said decoded output terminal.

Claim 6

A decoder circuit, as claimed in claim 4, wherein all of the drains of said current supply transistors are commonly connected to one point of said plurality of connection points.

Claim 7

A decoder circuit, as claimed in claim 5, wherein all of the drains of said current supply transistors are commonly connected to the nearest connection point of said decoded output terminal in said connection points.

Claim 8

A decoder circuit, as claimed in claim 4, wherein each of the drains of said current supply transistors is respectively connected to corresponding connection points, and when a specific decoder transitor is switched OFF, the connection points from said specific decoder transistor to said decoded output terminal are supplied with a current by said current supply transistors in accordance with the input signals except the nearest input signal.

Claim 9

A decoder circuit, as claimed in claim 7, wherein said corresponding connection points are determined as drains of said decoder transistors whose gates are supplied with the same input signals except the nearest input signal of said decoded output terminal supplied to the gates of said current supply transistors.

Claim 10

A decoder circuit, as claimed in claim 1, wherein said load means is used as a constant current source.

Claim 11

A decoder circuit, as claimed in claim 1, wherein said load means is formed by a depletion mode n-channel MOS transistor.

Claim 12

A decoder circuit, as claimed in claim 1, wherein said decoder circuit is provided in a row decoder of said programmable read only memory.

Claim 13

A programmable read only memory, comprising: a cell matrix portion, having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected between each of said word lines and each of said bit lines; a column decoder, connected to said cell matrix portion through said bit lines, for selecting one of said bit lines in accordance with address signals; a row decoder, connected to said cell matrix portion through said word lines, for selecting one of said word lines in accordance with address signals; a sense amplifier, connected to said cell matrix portion through said bit lines, for sensing a content of the selected memory cell; a data input buffer and program control circuit, connected to said cell matrix portion through said bit lines, for storing write data and supplying said write date to said cell matrix portion; an output enable and chip enable circuit, connected to said data input buffer and program control circuit, said column decoder, said row decoder, and said sense amplifier, for controlling them; and a high potential power supply means, for selectively supplying a high voltage and a low voltage between a writing time and a reading-out time through a high potential power supply line; wherein said row decoder includes a decoder circuit comprising: a low potential power supply line; a load means connected between said first high potential power supply line and a decoded output terminal; a plurality of decoder transistors, connected in series between said decoded output terminal and said low potential power supply line, and gates of said decoder transistors being supplied with input signals; a current supply means, connected to at least one of a plurality of connection points of said decoder transistors, for supplying a current to said at least one of said connection points, when at least one of said decoder transistors except the nearest decoder transistor of said decoded output terminal is switched OFF.

Claim 14

A programmable read only memory, comprising: a cell matrix portion, having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected between each of said word lines and each of said bit lines; a column decoder, connected to said cell matrix portion through said bit lines, for selecting one of said bit lines in accordance with address signals; a row decoder, connected to said cell matrix portion through said word lines, for selecting one of said word lines in accordance with address signals; a sense amplifier, connected to said cell matrix portion through said bit lines, for sensing a content of the selected memory cell; a data input buffer and program control circuit, connected to said cell matrix portion through said bit lines, for storing write data and supplying said write date to said cell matrix portion; an output enable and chip enable circuit, connected to said data input buffer and program control circuit, said column decoder, said row decoder, and said sense amplifier, for controlling them; and a high potential power supply means, for selectively supplying a high voltage and a low voltage between a writing time and a reading-out time through a high potential power supply line; wherein said row decoder includes a decoder circuit comprising: a low potential power supply line; a load means connected between said first high potential power supply line and a decoded output terminal; a plurality of decoder transistors, connected in series between said decoded output terminal and said low potential power supply line, and gates of said decoder transistors being supplied with input signals; a current supply means, connected to at least one of a plurality of connection points of said decoder transistors, for supplying a current to said at least one of said connection points, when at least one of said decoder transistors except the nearest decoder transistor of said decoded output terminal is switched OFF.

Claim 15

A programmable read only memory, as claimed in claim 12, wherein said current supply means is connected to one point of said plurality of connection points.

Claim 16

A programmable read only memory, as claimed in claim 13, wherein said current supply means is connected to the nearest connection point of said decoded output terminal in said connection points.

Claim 17

A programmable read only memory, as claimed in claim 12, wherein said decoder transistors are formed by first conduction type MOS transistors; said current supply means comprises a plurality of current supply transistors formed by second conduction type MOS transistors opposite to said first conduction type, sources of said current supply transistors are connected to a second high potential power supply line for supplying said low voltage, drains of said current supply transistors are connected to said at least one of said connection points, and gates of said current supply transistors are supplied with the input signals except the nearest input signal received by the nearest decoder transistor of said decoded output terminal.

Claim 18

A programmable read only memory, as claimed in claim 15, wherein all of the drains of said current supply transistors are commonly connected to one point of said plurality of connection points.

Claim 19

A programmable read only memory, as claimed in claim 16, wherein all of the drains of said current supply transistors are commonly connected to the nearest connection point of said decoded output terminal in said connection points.

Claim 20

A programmable read only memory, as claimed in claim 15, wherein each of the drains of said current supply transistors is respectively connected to corresponding connection points, and when a specific decoder transitor is switched OFF, the connection points from said specific decoder transistor to said decoded output terminal are supplied with a current by said current supply transistors in accordance with the input signals except the nearest input signal.

Claim 21

A programmable read only memory, as claimed in claim 18, wherein said corresponding connection points are determined as drains of said decoder transistors whose gates are supplied with the same input signals except the nearest input signal of said decoded output terminal supplied to the gates of said current supply transistors.

Claim 22

A programmable read only memory, as claimed in claim 12, wherein said load means is formed by a depletion mode n-channel MOS transistor.

Claim 23

A programmable read only memory, as claimed in claim 12, wherein each of said memory cells is formed by a floating gate avalanche injection MOS transistor.