US5214496A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1989-12-19
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Granted: 1993-05-25
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Expires: 2009-12-19
Abstract
Abstract A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
Inventors
- 👤 Hideo Sunami
- 👤 Tokuo Kure
- 👤 Masanobu Miyao
- 👤 Yoshifumi Kawamoto
- 👤 Katsuhiro Shimohigashi
- 👤 Yoshio Sakai
- 👤 Osamu Minato
- 👤 Toshiaki Masuhara
- 👤 Mitsumasa Koyanagi
- 👤 Shinji Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:02
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B12/39; H10B12/395; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
138 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate, said substrate being common to said plurality of memory cells, said semiconductor region having a first conductivity type, and said substrate having a second conductivity type, wherein said capacitor comprises: a first electrode formed as a region which includes a part of said substrate, said first electrode being formed around a portion of a groove in said semiconductor region; a second electrode being formed within said groove, said second electrode being coupled to a source or the drain of said insulated-gate field-effect transistor; and a first insulating film formed within said groove between said first electrode and said second electrode.
Claim 2
Dependent Claim
138 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate, said substrate being common to said plurality of memory cells, said semiconductor region having a first conductivity type, and said substrate having a second conductivity type, wherein said capacitor comprises: a first electrode formed as a region which includes a part of said substrate, said first electrode being formed around a portion of a groove in said semiconductor region; a second electrode being formed within said groove, said second electrode being coupled to a source or the drain of said insulated-gate field-effect transistor; and a first insulating film formed within said groove between said first electrode and said second electrode.
Claim 3
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises a single layer of SiO 2 .
Claim 4
Dependent Claim
22 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises a single layer of Si 3 N 4 .
Claim 5
Dependent Claim
22 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises a single layer of Ta 2 O 5 .
Claim 6
Dependent Claim
25 words
A semiconductor memory according to claim 1, wherein said first insulating layer comprises a composite layer of SiO 2 and Si 3 N 4 .
Claim 7
Dependent Claim
31 words
A semiconductor memory according to claim 1, wherein said part of said substrate included in said first electrode has an impurity concentration greater than that of another part of said substrate.
Claim 8
Dependent Claim
27 words
A semiconductor memory according to claim 1, wherein said substrate is coupled to a ground potential to serve as ground for said capacitors of said memory cells.
Claim 9
Dependent Claim
14 words
A semiconductor memory according to claim 1, wherein said second electrode comprises polycrystalline silicon.
Claim 10
Dependent Claim
15 words
A semiconductor memory according to claim 1, wherein said semiconductor region in an epitaxial layer.
Claim 11
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein said plurality of memory cells are arranged in an open-bit line structure.
Claim 12
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein said plurality of memory cells are arranged in a folded-bit line structure.
Claim 13
Dependent Claim
122 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate, said semiconductor region having a first conductivity type, and said substrate having a second conductivity type, wherein said capacitor comprises: a groove formed in the semiconductor region; a first insulating film formed within said groove; and a capacitor electrode being formed on said first insulating film, said capacitor electrode being coupled to a source or a drain of said insulated-gate field-effect transistor, wherein said substrate is coupled to a first potential to serve as a plate electrode for said capacitors of said memory cells.
Claim 14
Dependent Claim
122 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate, said semiconductor region having a first conductivity type, and said substrate having a second conductivity type, wherein said capacitor comprises: a groove formed in the semiconductor region; a first insulating film formed within said groove; and a capacitor electrode being formed on said first insulating film, said capacitor electrode being coupled to a source or a drain of said insulated-gate field-effect transistor, wherein said substrate is coupled to a first potential to serve as a plate electrode for said capacitors of said memory cells.
Claim 15
Dependent Claim
20 words
A semiconductor memory according to claim 12, wherein said first insulating film comprises a single layer of SiO 2 .
Claim 16
Dependent Claim
22 words
A semiconductor memory according to claim 12, wherein said first insulating film comprises a single layer of Si 3 N 4 .
Claim 17
Dependent Claim
22 words
A semiconductor memory according to claim 12, wherein said first insulating film comprises a single layer of Ta 2 O 5 .
Claim 18
Dependent Claim
25 words
A semiconductor memory according to claim 12, wherein said first insulating film comprises a composite layer of SiO 2 and Si 3 N 4 .
Claim 19
Dependent Claim
31 words
A semiconductor memory according to claim 12, further comprising: a first impurity region formed around a portion of the groove, wherein said first impurity region is electrically coupled to the substrate.
Claim 20
Dependent Claim
22 words
A semiconductor memory according to claim 17, wherein said first impurity region has an impurity concentration greater than that of said substrate.
Claim 21
Dependent Claim
14 words
A semiconductor memory according to claim 12, wherein said capacitor electrode comprises polycrystalline silicon.
Claim 22
Dependent Claim
15 words
A semiconductor memory according to claim 12, wherein said semiconductor region is an epitaxial layer.
Claim 23
Dependent Claim
14 words
A semiconductor memory according to claim 12, wherein said first potential is ground potential.
Claim 24
Dependent Claim
20 words
A semiconductor memory according to claim 12, wherein said plurality of memory cells are arranged in an open-bit line structure.
Claim 25
Dependent Claim
20 words
A semiconductor memory according to claim 12, wherein said plurality of memory cells are arranged in a folded-bit line structure.
Claim 26
Dependent Claim
160 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed above a substrate, wherein said insulated-gate field-effect transistor is formed on a semiconductor region of a first conductivity type, wherein said substrate is common to said plurality of memory cells and has a second conductivity, and wherein said semiconductor region is formed on said substrate, wherein said capacitor comprises: a first electrode formed as a region which includes a part of said substrate, a second electrode formed above said part of said substrate, said second electrode being connected to a source or the drain of said insulated-gate field-effect transistor; and a first insulating film formed only between said first electrode and said second electrode, wherein said substrate is coupled to a first potential to serve as at least a part of said first electrode for said capacitors of said memory cells.
Claim 27
Dependent Claim
160 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed above a substrate, wherein said insulated-gate field-effect transistor is formed on a semiconductor region of a first conductivity type, wherein said substrate is common to said plurality of memory cells and has a second conductivity, and wherein said semiconductor region is formed on said substrate, wherein said capacitor comprises: a first electrode formed as a region which includes a part of said substrate, a second electrode formed above said part of said substrate, said second electrode being connected to a source or the drain of said insulated-gate field-effect transistor; and a first insulating film formed only between said first electrode and said second electrode, wherein said substrate is coupled to a first potential to serve as at least a part of said first electrode for said capacitors of said memory cells.
Claim 28
Dependent Claim
20 words
A semiconductor memory according to claim 24, wherein said first insulating film comprises a single layer of SiO 2 .
Claim 29
Dependent Claim
22 words
A semiconductor memory according to claim 24, wherein said first insulating film comprises a single layer of Si 3 N 4 .
Claim 30
Dependent Claim
23 words
A semiconductor memory according to claim 24, wherein s said first insulating film comprises a single layer of Ta 2 O 5 .
Claim 31
Dependent Claim
25 words
A semiconductor memory according to claim 24, wherein said first insulating film comprises a composite layer of SiO 2 and Si 3 N 4 .
Claim 32
Dependent Claim
31 words
A semiconductor memory according to claim 24, wherein said part of said substrate included in said first electrode has an impurity concentration greater than that of another part of said substrate.
Claim 33
Dependent Claim
14 words
A semiconductor memory according to claim 24, wherein said first potential is ground potential.
Claim 34
Dependent Claim
14 words
A semiconductor memory according to claim 24, wherein said second electrode comprises polycrystalline silicon.
Claim 35
Dependent Claim
15 words
A semiconductor memory according to claim 24, wherein said semiconductor region is an epitaxial layer.
Claim 36
Dependent Claim
20 words
A semiconductor memory according to claim 24, wherein said plurality of memory cells are arranged in an open-bit line structure.
Claim 37
Dependent Claim
20 words
A semiconductor memory according to claim 24, wherein said plurality of memory cells are arranged in a folded-bit line structure.
Claim 38
Dependent Claim
208 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate which substrate is common to said plurality of memory cells, said semiconductor region having a first conductivity type, wherein said capacitor comprises: a first electrode formed as a sidewall of a groove formed in said substrate and said semiconductor region, said groove extending through said semiconductor region into said substrate; a first insulating film formed within said groove over said first electrode; and a second electrode formed within said groove over said first insulating film, said second electrode being connected to the source or the drain of said insulated-gate field-effect transistor, wherein said substrate has an impurity concentration greater than that of said semiconductor region, and wherein a third electrode is provided on said second electrode with a second insulating film being interposed between the second and third electrodes, said third electrode being located to form a second capacitor comprised of said third electrode, said second insulating film and said second electrode in parallel with said capacitor formed by said first electrode, said first insulating film and said second electrode.
Claim 39
Dependent Claim
208 words
A semiconductor memory which includes a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a predetermined semiconductor region formed on a substrate which substrate is common to said plurality of memory cells, said semiconductor region having a first conductivity type, wherein said capacitor comprises: a first electrode formed as a sidewall of a groove formed in said substrate and said semiconductor region, said groove extending through said semiconductor region into said substrate; a first insulating film formed within said groove over said first electrode; and a second electrode formed within said groove over said first insulating film, said second electrode being connected to the source or the drain of said insulated-gate field-effect transistor, wherein said substrate has an impurity concentration greater than that of said semiconductor region, and wherein a third electrode is provided on said second electrode with a second insulating film being interposed between the second and third electrodes, said third electrode being located to form a second capacitor comprised of said third electrode, said second insulating film and said second electrode in parallel with said capacitor formed by said first electrode, said first insulating film and said second electrode.
Claim 40
Dependent Claim
27 words
A semiconductor memory according to claim 35, wherein said substrate is coupled to a ground potential to serve as ground for said capacitors of said memory cells.
Claim 41
Dependent Claim
17 words
A semiconductor memory according to claim 35, wherein said semiconductor region is grown epitaxially on said substrate.
Claim 42
Dependent Claim
24 words
A semiconductor memory according to claim 35, wherein a portion of said second insulating film and said third electrode are formed within the groove.
Claim 43
Dependent Claim
54 words
A semiconductor memory according to claim 38, wherein said third electrode has a T-configuration with a top portion extending parallel to a major surface of said semiconductor region in which said groove is formed and a lower portion extending from said top portion into said groove in a direction perpendicular to said major surface.
Claim 44
Dependent Claim
24 words
A semiconductor memory according to claim 35, further comprising a high impurity region formed in said semiconductor region at said sidewall of said groove.
Claim 45
Dependent Claim
34 words
A semiconductor memory according to claim 35, wherein said first insulating film, said second electrode, and second insulating film and said third electrode extend over at least a portion of said insulated-gate field-effect transistor.
Claim 46
Dependent Claim
41 words
A semiconductor memory according to claim 41, wherein said first insulating film, said electrode, said second insulating film and said third electrode extend over a gate and at least one of the source and drain regions of said insulated-gate field-effect transistors.
References Cited (Backward Citations)
US3962713A
Cited
JPS5454588A
Cited
US4432006A
Cited
JPS5643171A
Cited
JPS5667957A
Cited
US4327476A
Cited
JPS5685965A
Cited
JPS583260A
Cited
JPS583261A
Cited
JPS58137245A
Cited
JPS58154256A
Cited
JPS6046067A
Cited
JPS6058663A
Cited
JPS60103665A
Cited
JPS60109265A
Cited
JPS60113460A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |