Monotonic pulse detector

Claim 1

A peak detector circuit for generating output pulses corresponding to monotonically increasing amplitude peaks of a differential input signal, comprising: first means for detecting monotonic increases in amplitude of the differential input signal and providing a digital output signal having a first logic state while the differential input signal monotonically increases, said first means including a first peak detector having a signal input, a reset input and an output, said signal input being coupled for receiving a first component of the differential input signal, said output maintaining an output signal at a maximum amplitude of said first component of the differential input signal, said reset input being coupled for receiving a reset signal for initializing said output signal of said first peak detector to a predetermined low amplitude; second means coupled for receiving the differential input signal and generating clock signals at amplitude peaks of the differential input signal; third means for storing said digital output signal having said first logic state upon receiving said clock signals and resetting said third means after a predetermined time delay for developing the output pulses of the peak detector circuit, wherein a maximum peak of the monotonically increasing amplitude peaks of the differential input signal is identified by a most recent one of the output pulses of the peak detector circuit before said digital output signal changes to a second logic state which occurs as the differential input signal changes direction toward an opposite polarity; and fourth means for detecting a polarity of the differential input signal and generating an output polarity signal having a first logic state when the differential input signal is greater than a differential reference signal and a second logic state when the differential input signal is less than said differential reference signal, said output polarity signal providing said reset signal applied at said reset input of said first peak detector, said fourth means including, (a) a first comparator having first and second inputs and an output, said first input being coupled for receiving the differential input signal, said second input being coupled for receiving said differential reference signal, said output providing said output polarity signal of said fourth means, and (b) a first inverter having an input coupled to said output of said first comparator and having an output coupled to said reset input of said first peak detector.

Claim 3

A method of generating output pulses for a circuit corresponding to monotonically increasing amplitude peaks of a differential input signal, comprising the steps of: detecting monotonic increases in amplitude of the differential input signal and providing a first digital output signal having a first logic state while the differential input signal monotonically increases above a first predetermined threshold; developing clock signals at amplitude peaks of the differential input signal; and storing said first digital output signal having said first logic state upon receiving said clock signals such that a maximum peak of the monotonically increasing amplitude peaks of the differential input signal is identified by a most recent one of the output pulses of the circuit before said first digital output signal changes to a second logic state which occurs as the differential input signal goes below a second predetermined threshold.

Claim 4

A method of generating output pulses for a circuit corresponding to monotonically increasing amplitude peaks of a differential input signal, comprising the steps of: detecting monotonic increases in amplitude of the differential input signal and providing a first digital output signal having a first logic state while the differential input signal monotonically increases above a first predetermined threshold; developing clock signals at amplitude peaks of the differential input signal; and storing said first digital output signal having said first logic state upon receiving said clock signals such that a maximum peak of the monotonically increasing amplitude peaks of the differential input signal is identified by a most recent one of the output pulses of the circuit before said first digital output signal changes to a second logic state which occurs as the differential input signal goes below a second predetermined threshold.