Patent US5212413A successfully refreshed from Google Patents.
US5212413A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stable, programmable low-dissipation reference circuit
Assignee: US Philips Corp
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Filing: 1991-07-08
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Granted: 1993-05-18
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Expires: 2011-07-08
Abstract
Abstract When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.
Inventors
- 👤 Cathal G. Phelan
- 👤 Peter H. Voss
- 👤 Thomas J. Davies
- 👤 Cormac M. O'Connell
- 👤 Leonardus C. M. G. Pfennings, deceased
- 👤 legal representative Henricus J. Kunnen
- 👤 Hans Ontrop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:42
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
88 words
A programmable reference circuit which, prior to programming, is in a first and after programming in a second logic state and which includes a first and a second cross-wise coupled inverter which are each connected between two power supply lines, the first inverter including an active element and a programmable element connected in series therewith, characterized in that a second active element whose control electrode is directly and continuously connected to one of the supply lines is arranged in parallel with the active element of the first inverter.
Claim 2
Dependent Claim
88 words
A programmable reference circuit which, prior to programming, is in a first and after programming in a second logic state and which includes a first and a second cross-wise coupled inverter which are each connected between two power supply lines, the first inverter including an active element and a programmable element connected in series therewith, characterized in that a second active element whose control electrode is directly and continuously connected to one of the supply lines is arranged in parallel with the active element of the first inverter.
Claim 3
Dependent Claim
90 words
An integrated circuit comprising a memory, in which a plurality of reference circuits having outputs for setting redundancy circuits for substitution of defective rows of columns of memory cells of the memory are provided, characterized in that a first reference circuit is the reference circuit as claimed in claim 1 and that further reference circuits are provided, in which reference circuits a second active element, whose control electrode is coupled to an output of the first reference circuit, is arranged in parallel with the active element of the first inverter.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |