Non-aligned DRAM state machine for page-mode DRAM control

Claim 2

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having a frequency m times the frequency of the first clock, an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: means, coupled to a state machine of said component controller, and adapted to receive signals identifying an n-1 through n-m states of a component access cycle having n state transitions, for sampling for said n-1 through n-m states on a given edge of said first clock; and means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.

Claim 3

The component controller of claim 1 wherein said component is a DRAM.

Claim 4

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having twice the frequency of the first clock, an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: means, coupled to a state machine of said component controller and adapted to receive signals, for identifying an n-1 and n-2 states of a component access cycle having n state transitions, for sampling at said n-1 and n-2 states on a given edge of said first clock; and means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 and n-2 states is detected.

Claim 5

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having twice the frequency of the first clock, an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: means, coupled to a state machine of said component controller and adapted to receive signals, for identifying an n-1 and n-2 states of a component access cycle having n state transitions, for sampling at said n-1 and n-2 states on a given edge of said first clock; and means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 and n-2 states is detected.

Claim 6

The component controller of claim 3 wherein said component is a DRAM.

Claim 7

In a microprocessor system operating according to a first clock, a controller device for controlling a system component comprising: a programmable register for storing a plurality of variables, wherein said variable describe a given set of timing options; a state machine that transitions through a series of states to output a plurality of timing signals to said system component, and coupled to said programmable register, to said system component and to a second clock having a frequency different from said first clock; and a ready circuit, coupled to said first clock, aid state machine and said programmable register, for sampling said series of states and for asserting a ready signal when a specified state is detected on a given edge of said first clock to synchronize said state machine with said first clock at the end of a component access cycle.

Claim 8

In a microprocessor system operating according to a first clock, a controller device for controlling a system component comprising: a programmable register for storing a plurality of variables, wherein said variable describe a given set of timing options; a state machine that transitions through a series of states to output a plurality of timing signals to said system component, and coupled to said programmable register, to said system component and to a second clock having a frequency different from said first clock; and a ready circuit, coupled to said first clock, aid state machine and said programmable register, for sampling said series of states and for asserting a ready signal when a specified state is detected on a given edge of said first clock to synchronize said state machine with said first clock at the end of a component access cycle.

Claim 9

The component controller of claim 5 wherein said component is a DRAM.

Claim 10

In a microprocessor system including a microprocessor operating according to a first clock and a system component, a component controller comprising: means for storing a given set of component timing options; a state machine for transitioning through a series of states to output a plurality of timing signals to said system component and coupled to said means for storing and to a second clock having a frequency m times the frequency of the first clock; and an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle having: (i) means, coupled to a state machine of said component controller and adapted to receive signals, identifying an n-1 through n-m states of a component access cycle having n state transitions, for sampling at each of said n-1 through n-m states on a given edge of said first clock; and (iii) means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.

Claim 11

In a microprocessor system including a microprocessor operating according to a first clock and a system component, a component controller comprising: means for storing a given set of component timing options; a state machine for transitioning through a series of states to output a plurality of timing signals to said system component and coupled to said means for storing and to a second clock having a frequency m times the frequency of the first clock; and an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle having: (i) means, coupled to a state machine of said component controller and adapted to receive signals, identifying an n-1 through n-m states of a component access cycle having n state transitions, for sampling at each of said n-1 through n-m states on a given edge of said first clock; and (iii) means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.

Claim 12

The component controller of claim 7 wherein said component is a DRAM.

Claim 13

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having a frequency m times the frequency of the first clock, a method for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: identifying an n-1 through n-m states of a component access cycle having n state transitions; sampling for each of said n-1 through n-m states on a given edge of said first clock; and asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.

Claim 14

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having a frequency m times the frequency of the first clock, a method for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: identifying an n-1 through n-m states of a component access cycle having n state transitions; sampling for each of said n-1 through n-m states on a given edge of said first clock; and asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.

Claim 15

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having twice the frequency of the first clock, a method for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: identifying an n-1 and n-2 states of a component access cycle having n state transitions; sampling for said n-1 and n-2 states on a given edge of said first clock; and asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-2 state is detected.

Claim 16

In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having twice the frequency of the first clock, a method for synchronizing said component controller to said first clock at the completion of a component access cycle comprising: identifying an n-1 and n-2 states of a component access cycle having n state transitions; sampling for said n-1 and n-2 states on a given edge of said first clock; and asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-2 state is detected.

Claim 17

In a microprocessor system including a microprocessor operating according to a first clock and a system component, a method for operating a component controller comprising the steps of: storing a given set of component timing options; transitioning through a series of states using a state machine to output a plurality of timing signals to said system component according to said given set of timing options; operating said state machine using a secondary clock having a frequency m times the frequency of the first clock; and synchronizing said component controller to said first clock at the completion of a component access cycle wherein said step of synchronizing includes the steps of: (i) identifying an n-1 through n-m states of a component access cycle having n state transitions; (ii) sampling for each of said n-1 through n-m states on a given edge of said first clock; and (iii) asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-2 states is detected.

Claim 18

In a microprocessor system including a microprocessor operating according to a first clock and a system component, a method for operating a component controller comprising the steps of: storing a given set of component timing options; transitioning through a series of states using a state machine to output a plurality of timing signals to said system component according to said given set of timing options; operating said state machine using a secondary clock having a frequency m times the frequency of the first clock; and synchronizing said component controller to said first clock at the completion of a component access cycle wherein said step of synchronizing includes the steps of: (i) identifying an n-1 through n-m states of a component access cycle having n state transitions; (ii) sampling for each of said n-1 through n-m states on a given edge of said first clock; and (iii) asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-2 states is detected.