US5210716A — Semiconductor nonvolatile memory

Claim 1

Independent Claim 275 words

A semiconductor nonvolatile memory device comprising: a plurality of memory arrays for effecting nonvolatile data storage in terms of two different stable states corresponding to a binary signal in the form of "1" and "0"; a peripheral circuit for driving selectively each memory array to effect addressing and reading; and a control circuit operative when a selected memory array reaches an operational limit of rewriting cycle number to switch to another memory array to thereby ensure continuous operation of the device, the control circuit comprising: (a) a storing control circuit for receiving a data writing signal from a data store terminal to generate signals, (b) a storing pulse generating circuit responsive to one of the signals from the storing control circuit for generating a storing pulse, (c) a memory array switching circuit responsive to the storing pulse for relaying the storing pulse and responsive to one of the signals from the storing control circuit for switching memory arrays, (d) a "1"/"0" generating circuit responsive to one of the signals from the storing control circuit for generating a "1" or "0" data signal alternatively, (e) monitor elements responsive to the "1" or "0" signal from the "1"/"0" generating circuit for generating a writing level, (f) a writing level detection circuit for detecting the writing level of one of the monitor elements and outputting a signal to the storing control circuit according to the writing level of said one of the monitor elements, and (g) a monitor element switching circuit for relaying the storing pulse to one of the monitor elements and responsive to one of the signals from the storing control circuit for switching monitor elements.

Claim 2

Dependent Claim 275 words

A semiconductor nonvolatile memory device comprising: a plurality of memory arrays for effecting nonvolatile data storage in terms of two different stable states corresponding to a binary signal in the form of "1" and "0"; a peripheral circuit for driving selectively each memory array to effect addressing and reading; and a control circuit operative when a selected memory array reaches an operational limit of rewriting cycle number to switch to another memory array to thereby ensure continuous operation of the device, the control circuit comprising: (a) a storing control circuit for receiving a data writing signal from a data store terminal to generate signals, (b) a storing pulse generating circuit responsive to one of the signals from the storing control circuit for generating a storing pulse, (c) a memory array switching circuit responsive to the storing pulse for relaying the storing pulse and responsive to one of the signals from the storing control circuit for switching memory arrays, (d) a "1"/"0" generating circuit responsive to one of the signals from the storing control circuit for generating a "1" or "0" data signal alternatively, (e) monitor elements responsive to the "1" or "0" signal from the "1"/"0" generating circuit for generating a writing level, (f) a writing level detection circuit for detecting the writing level of one of the monitor elements and outputting a signal to the storing control circuit according to the writing level of said one of the monitor elements, and (g) a monitor element switching circuit for relaying the storing pulse to one of the monitor elements and responsive to one of the signals from the storing control circuit for switching monitor elements.

Claim 3

Dependent Claim 65 words

A semiconductor nonvolatile memory device, comprising: a plurality of memory arrays; a peripheral circuit for selectively driving each memory array to effect addressing and reading; and control circuit means for determining when an operational limit of rewriting cycles of a selected memory array has been reached and then switching from the selected memory array to another memory array to be driven by the peripheral circuit.

Claim 4

Dependent Claim 65 words

A semiconductor nonvolatile memory device, comprising: a plurality of memory arrays; a peripheral circuit for selectively driving each memory array to effect addressing and reading; and control circuit means for determining when an operational limit of rewriting cycles of a selected memory array has been reached and then switching from the selected memory array to another memory array to be driven by the peripheral circuit.

Claim 5

Dependent Claim 77 words

A memory device according to claim 2, wherein the control circuit means includes a plurality of monitoring elements corresponding to and having the same construction as a respective memory array, a data generating circuit for writing a data signal to one of the monitoring elements with each rewriting cycle of the corresponding memory arrays, and a writing level detection circuit responsive to the monitoring elements for detecting when the operational limit of rewriting cycles has been reached.

Claim 6

Dependent Claim 41 words

A memory device according to claim 3, wherein the data generating circuit has means for writing the data signal with each rewriting cycle so as to have a different value from the data signal written during the just previous rewriting cycle.

Claim 7

Dependent Claim 42 words

A memory device according to claim 2, wherein the control circuit means includes a nonvolatile counter for accumulatively counting a predetermined number of rewriting cycles of the selected memory array to determine when the operational limit of rewriting cycles has been reached.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-05-10	1996-11-09	1997-05-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-05-10	2000-11-09	2001-05-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-05-10	2004-11-09	2005-05-11	$7700.00	Window Closed / Lapsed

Semiconductor nonvolatile memory

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