Resistive gate magnetic field sensor

Claim 2

A FET device for sensing a magnetic field, said FET device comprising: a semiconductor material having a source at a first position therein and receiving means at a second position therein for receiving charge carriers; bias voltage means for providing a bias voltage between said source and said receiving means to produce a movement of charge carriers in a direction between said source and said receiving means; a channel layer disposed within said semiconductor material between said source and said receiving means through which said charge carriers move in said direction as a function of said bias voltage, and said magnetic field being sensed having a strength and producing a deflection of said charge carriers from said direction, which deflection varies as a function of the strength of said magnetic field being sensed; a resistive gate having first and second resistive gate contacts respectively disposed at first and second ends of said resistive gate, said resistive gate disposed between said source and said receiving means and above said channel layer; resistive gate voltage means for providing a resistive gate bias voltage between said first and second resistive gate contacts to establish a longitudinal electric field in said channel layer; and output means coupled to said receiving means for providing a signal related to the deflection of the charge carriers that is produced by the strength of the magnetic field sensed by said FET device.

Claim 3

The FET device of claim 1 wherein: said resistive gate is located above said channel layer; said first resistive gate contact is disposed in a portion of said resistive gate nearest to said source; and said second resistive gate contact is disposed in a portion of said resistive gate nearest to said receiving means.

Claim 4

The FET device of claim 1 wherein: said receiving means includes first and second drains adjacently positioned at said second preselected position, said first and second drains respectively having first and second outputs, and said second preselected position is on a side of said second resistive gate furtherest away from said source; and said output means is coupled to said first and second outputs for providing the signal related to the deflection of the charge carriers that is produced by the strength of the magnetic field being sensed by the FET device.

Claim 5

The FET device of claim 3 further including: charge splitter means, disposed between said first and second drains and extending into a region of high longitudinal electric field in said channel layer beneath said resistive gate, for preventing charge carrier buildup in and near the region between said first and second drains.

Claim 6

The FET device of claim 4 wherein: said charge splitter means is selected from the group consisting of a region of heavily doped P-type material, a region of thicker insulator and a region of proton ion damaged semiconductor material, for the prevention of charge carrier buildup in and near the region between said first and second drains.

Claim 7

The FET device of claim 4 wherein said output means includes: means coupled to said first and second drains for producing a signal related to the deflection of the charge carriers that is produced by the strength of the magnetic field sensed by the FET device.

Claim 8

The FET device of claim 3 wherein: said source and drains are self aligned to said resistive gate disposed beneath said first and second resistive gate contacts.

Claim 9

The FET device of claim 3 wherein: said output means comprises a MOSFET source follower load connected to each of said first and second drains.

Claim 10

The FET device of claim 3 wherein: said first and second resistive gate contacts are disposed at said first and second preselected positions and substantially between said source and said drains.

Claim 11

The FET device of claim 1 wherein: said semiconductor material is selected from the group consisting of a silicon semiconductor material, a GaAs semiconductor material, a column III-column V material, and a combination thereof.

Claim 12

The FET device of claim 1 wherein: said resistive gate is comprised of a material selected from the group consisting of cermet, lightly doped polysilicon and undoped polysilicon.

Claim 13

The FET device of claim 1 wherein: said channel layer is a heterostructure consisting of a semiconductor material of one bandgap and a second semiconductor material of a wider bandgap.

Claim 14

The FET device of claim 1 wherein: a first portion of said semiconductor material is an N-type layer of semiconductor material and a second portion of said semiconductor material is selected from the group consisting of a P-type semi-insulating semiconductor material and a semi-insulating semiconductor material; and said channel layer is disposed within said N-type layer of semiconductor material.

Claim 15

The FET device of claim 1 further including: an insulating layer disposed between said semiconductor material and said resistive gate.

Claim 16

The FET device of claim 14 wherein: said insulating layer is selected from the group consisting of silicon dioxide, silicon nitride, a wide bandgap semiconductor material, and a combination thereof.

Claim 17

The FET device of claim 1 wherein: each of said first and second resistive gate contacts is selected from the group consisting of ohmic metal and heavily doped polysilicon.

Claim 18

A FET device for sensing a magnetic field, said FET device comprising: a semiconductor material having a source at a first position therein and receiving means at a second position therein for receiving charge carriers; bias voltage means for providing a bias voltage between said source and said receiving means to produce a movement of charge carriers in a direction between said source and said receiving means; a channel layer disposed within said semiconductor material between said source and said receiving means through which said charge carriers move in said direction as a function of said bias voltage, and said magnetic field being sensed having a strength and producing a deflection of said charge carriers from said direction, which deflection varies as a function of the strength of said magnetic field being sensed; a resistive gate having first and second resistive gate contacts respectively disposed at first and second ends of said resistive gate, said resistive gate disposed between said source and said receiving means and above said channel layer; resistive gate voltage means for providing a resistive gate bias voltage between said first and second resistive gate contacts to establish a longitudinal electric field in said channel layer; and output means comprising first and second electrode means, disposed in said semiconductor material and on opposite sides of said resistive gate, for producing output voltage signals related to the deflection of said charge carriers within said channel layer, which deflection is produced by the strength of the magnetic field sensed by said FET device.

Claim 19

A FET device for sensing a magnetic field, said FET device comprising: a semiconductor material having a source at a first position therein and receiving means at a second position therein for receiving charge carriers; bias voltage means for providing a bias voltage between said source and said receiving means to produce a movement of charge carriers in a direction between said source and said receiving means; a channel layer disposed within said semiconductor material between said source and said receiving means through which said charge carriers move in said direction as a function of said bias voltage, and said magnetic field being sensed having a strength and producing a deflection of said charge carriers from said direction, which deflection varies as a function of the strength of said magnetic field being sensed; a resistive gate having first and second resistive gate contacts respectively disposed at first and second ends of said resistive gate, said resistive gate disposed between said source and said receiving means and above said channel layer; resistive gate voltage means for providing a resistive gate bias voltage between said first and second resistive gate contacts to establish a longitudinal electric field in said channel layer; and output means comprising first and second electrode means, disposed in said semiconductor material and on opposite sides of said resistive gate, for producing output voltage signals related to the deflection of said charge carriers within said channel layer, which deflection is produced by the strength of the magnetic field sensed by said FET device.

Claim 20

The FET device of claim 17 wherein: said channel layer is a heterostructure comprised of a semiconductor material of one bandgap and a second semiconductor material of a wider bandgap.

Claim 21

The FET device of claim 17 wherein: a first portion of said semiconductor material is an N-type layer of semiconductor material and a second portion of said semiconductor material is a P-type semiconductor material; and said channel layer is disposed within said N-type layer of semiconductor material.

Claim 22

The FET device of claim 17 further including: an insulating layer disposed between said semiconductor material and said resistive gate.

Claim 23

The FET device of claim 20 wherein: said insulating layer is selected from the group consisting of silicon dioxide, silicon nitride, a wide bandgap semiconductor material, and a combination thereof.

Claim 24

The FET device of claim 20 further including: a surface channel transport layer disposed in said semiconductor material and adjacent to said insulating layer.