Circuit configuration for digital bit-serial signal processing

Claim 2

A circuit configuration for digital bit-serial signal processing, comprising: n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right, sign repetition devices each being assigned to a respective one of said input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right; a serial arithmetic unit connected downstream of said input shift registers for serially outputting output data words; m output shift registers connected downstream of said serial arithmetic unit being written in serially with the output data words; a control unit connected to said serial arithmetic unit, once all of the output data words have been fully written in said respective output shift registers, said control unit ending a reading of said input shift registers and the writing in of said output shift registers, for resetting said arithmetic unit to a defined initial state, and for enabling said input shift registers for writing in new input data words; k feedback shift registers each being written-in in parallel with data words stored in said output shift registers and being read out serially for a further transmission of the data word to said arithmetic unit, said feedback shift register having a length at least as long as the longest occurring data word; and other sign repetition devices assigned to said feedback shift registers for continuously generating and shifting the algebraic sign of the data words onward.

Claim 3

The circuit configuration according to claim 1, wherein the writing in and reading out of said feedback shift registers is effected synchronously with the writing in and reading out of said input shift registers.

Claim 4

The circuit configuration according to claim 1, wherein said feedback shift registers and said output shift registers are lengthened by at least one bit for overflow monitoring.

Claim 5

The circuit configuration according to claim I, wherein said arithmetic unit has at least one full adder to which data words are input serially and from which data words are output serially, said at least one full adder having a transmission output and a transmission input, and including a register coupling the transmission output and transmission input of said full adder to one another, said register having an input side occupied by a logical zero at the defined initial state.

Claim 6

The circuit configuration according to claim 1, wherein said arithmetic unit has at least one full adder to which data words are input serially and from which data words are output serially, said at least one full adder having an input, a transmission output and a transmission input, and including an inverter connected upstream of the input of said at least one full adder, and a register coupling the transmission output and the transmission input of said at least one full adder to one another, said register having an input side being occupied by a logical one at a defined initial state.

Claim 7

The circuit configuration according to claim 1, wherein said arithmetic unit has at least one full adder with inputs, and including at least one delay element coupling one of the inputs to another of the inputs of said at least one full adder.

Claim 8

The circuit configuration according to claim 1, including a monitoring device connected to said output shift registers for checking the output data word as to whether a given values region has been adhered to, for passing on the output data word if the values region is adhered to, and for setting the output data word to a maximum value maintaining the same algebraic sign if the values region is not adhered to.

Claim 9

The circuit configuration according to claim 7, wherein the length of the output data word is shortened by said monitoring device.

Claim 10

A circuit configuration for digital bit-serial signal processing, comprising: n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right. sign repetition devices each being assigned to a respective one of said input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right; a serial arithmetic unit connected downstream of said input shift registers for serially outputting output data words; m output shift registers connected downstream of said serial arithmetic unit being written in serially with the output data words; a control unit connected to said serial arithmetic unit, once all of the output data words have been fully written in said respective output shift registers, said control unit ending a reading of said input shift registers and the writing in of said output shift registers, for resetting said arithmetic unit to a defined initial state, and for enabling said input shift registers for writing in new input data words; feedback shift registers into which data words being transferred from said arithmetic unit and supplied back to said arithmetic unit are written in serially by shifting to the right and simultaneously read out, said feedback shift registers each having a length at least as long as the longest occurring data word; and other sign repetition devices assigned to said feedback shift registers, and a multiplexer connected upstream of said feedback shift registers being imposed upon said other sign repetition devices and subsequently upon said arithmetic unit, upon writing in of said respective feedback shift registers for a certain number of least significant bits of the data words to be transferred, and signs generated and shifted onward by said other sign repetition devices being equal to signs of the data words to be read out.

Claim 11

A circuit configuration for digital bit-serial signal processing, comprising: n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right. sign repetition devices each being assigned to a respective one of said input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right; a serial arithmetic unit connected downstream of said input shift registers for serially outputting output data words; m output shift registers connected downstream of said serial arithmetic unit being written in serially with the output data words; a control unit connected to said serial arithmetic unit, once all of the output data words have been fully written in said respective output shift registers, said control unit ending a reading of said input shift registers and the writing in of said output shift registers, for resetting said arithmetic unit to a defined initial state, and for enabling said input shift registers for writing in new input data words; feedback shift registers into which data words being transferred from said arithmetic unit and supplied back to said arithmetic unit are written in serially by shifting to the right and simultaneously read out, said feedback shift registers each having a length at least as long as the longest occurring data word; and other sign repetition devices assigned to said feedback shift registers, and a multiplexer connected upstream of said feedback shift registers being imposed upon said other sign repetition devices and subsequently upon said arithmetic unit, upon writing in of said respective feedback shift registers for a certain number of least significant bits of the data words to be transferred, and signs generated and shifted onward by said other sign repetition devices being equal to signs of the data words to be read out.

Claim 12

The circuit configuration according to claim 9, wherein the reading out of said feedback shift registers is effected in synchronism with the reading out of said input shift register.

Claim 13

The circuit configuration according to claim 9, wherein said feedback shift registers and said output shift registers are lengthened by at least one bit for overflow monitoring.

Claim 14

The circuit configuration according to claim 9, wherein all of the places of said feedback shift register are set equal to zero at the defined initial state.