Serial digital signal processing circuitry

Claim 2

Apparatus for processing serial-bit two's complement digital signals occurring in equally spaced intervals with all bits of a sample occurring in less than a sample interval, comprising: a serial arithmetic processing unit (18) having an input and an output terminal; a serial shift register (20) having an input, an output and a clock input terminals; characterised by a sign-extend-register (14, 16) having an input, an output, a clock input and a sign-extend input terminal; means for serially coupling said serial shift register, said arithmetic processing unit and said sign extend register wherein said arithmetic processing unit is disposed between said registers; means for generating a first clock signal (22) having a first predetermined number of pulses per sample interval, a second clock signal having a second predetermined number of pulses per sample interval and a sign-extend signal occurring at the occurrence of a predetermined bit of said serial-bit digital samples; and means for coupling said first and second clock signals to the clock input terminals of said serial shift register and sign-extend register respectively, and means for coupling said sign-extend signal to said sign-extend input terminal.

Claim 3

The apparatus set forth in claim 1 wherein said serial arithmetic processing unit (SAPU) includes a binary adder comprising: a full adder circuit (36) having a first addend/augend input terminal coupled to the input terminal of said SAPU, a sum output terminal coupled to the output terminal of said SAPU, having a second addend/augend input terminal for applying a serial-bit sample, a carry-in and a carry-out terminal; and a one sample bit delay element (34) coupled between said carry-in and said carry-out terminals.

Claim 4

The apparatus set forth in claim 2 further including an inverter (33) interposed between the input terminal of the SAPU and said first addend/augend input terminal; and means (SET) to set said delay element to a one state at the beginning of each sample period wherein said full adder provides the difference between serial samples applied to its second and first addend/augend input terminals.

Claim 5

The apparatus set forth in claim 1 wherein said serial arithmetic processing unit (SAPU) includes a two's complementing circuit comprising: an inverter (45) serially coupled to the input terminal of said SAPU; a half-adder (46) having a first addend/augend input terminal serially coupled to said inverter, a second addend/augend input terminal, a sum output terminal coupled to the output terminal of said SAPU and a carry-out output terminal; a one sample bit period delay element (47) coupled between said carry-out output terminal and the second addend/augend input terminal; and means (SET) for setting said delay element to a one state at the beginning of each sample interval.

Claim 6

The apparatus set forth in claim 1 wherein the serial arithmetic processing unit (SAPU) includes a binary multiplier for multiplying serial-bit samples by 2 K , where K is an integer, comprising a K-stage shift register (26) coupled between the input and output terminals of said SAPU.

Claim 7

The apparatus set forth in claim 1 wherein said serial arithmetic processing unit (SAPU) includes an absolute value circuit (51,52,53,54,55) and the register (50) coupled to the input terminal of the SAPU includes a tap for providing a sign-bit of said two's complement samples at the beginning of each sample period, said absolute value circuit comprising: a latch (51) coupled to said tap for storing said sign bit; switch means (54) having an output terminal coupled to the output terminal of the SAPU, first and second data input terminals, and having a control terminal coupled to said latch, for alternatively applying samples applied to said first and second data input terminals for said sign-bit being a one or zero respectively; a serial-bit two's complement circuit (52) having an input terminal coupled to the input terminal of the SAPU, and an output terminal coupled to said first data input terminal; a compensating delay element (53) coupled between the input terminal of said SAPU and the second data input terminal, said compensating delay element providing a delay period equivalent to the processing delay of said two's complement circuit.

Claim 8

The apparatus set forth in claim 6 wherein the shift register (output register) coupled to the output terminal of the SAPU is merged into comparing means comprising: a first input terminal coupled to a predetermined stage of the output register (66), the number of stages between said predetermined stage and the output of said register being N in number where N is an integer, and a second input terminal for applying a serial-bit sample to be compared with samples applied to said first input terminal; an N-stage shift register (67) having an input terminal coupled to said second input terminal, and having an output terminal; further switch means (68) having first and second data input terminals coupled respectively to the output terminals of said output register and said N-stage register, a control input terminal, and an output terminal at which the greater of the samples applied to the first and second input terminals is produced; means (60,62,63,64,65) coupled to the first and second input terminals for producing a control signal exhibiting a first output state if the sample applied to the first input terminal exhibits a logic one in a more significant bit position, excluding sign bits, than the sample applied to the second input terminal, or the sample applied to the first input terminal is positive and the sample applied to the second input terminal is negative, and exhibits a second state otherwise; and a latch (70) for coupling said control signal to said further switch means, wherein said further switch means couples said output register or the N-stage register to its output terminal for the control signal exhibiting first and second state respectively.

Claim 9

The apparatus set forth in claim 7 wherein said means for producing a control signal comprises: first (60) and second (62) AND gates having respective non-inverting inputs coupled to said first and second input terminals respectively and having respective inverting inputs coupled to said second and first input terminals respectively and having respective output terminals; a JK flip-flop (63) having J and K input terminals respectively coupled to the output terminals of said first and second AND gates, respectively and having an output terminal; a third AND gate (64) having inverting and non-inverting input terminals coupled to the output terminals of said first AND gate and said JK flip-flop respectively, and having an output terminal; and an OR gate (65) having respective input terminals coupled to the output terminals of said third and second AND gates and an output terminal coupled to said latch.