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US5204545A Expired / Lapsed US ⏱️ 0.0 years remaining

Structure for preventing field concentration in semiconductor device and method of forming the same

Assignee: Mitsubishi Electric Corp
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Filing: 1991-12-17
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Granted: 1993-04-20
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Expires: 2011-12-17
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Abstract

Abstract There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p - substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p diffusion regions (18a, 18b) and the conductive plates (16a-16e) are alternately arranged and so aligned that adjacent pairs of end portions thereof overlap with each other. Capacitances of capacitive coupling of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) are optimized so that potentials of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) can substantially linearly change from a low level to a high level. Thus, the concentration of electric field can be prevented.

Inventors

  • 👤 Tomohide Terashima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 09:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D64/112

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 250 words
In a semiconductor device comprising a first conductivity type semiconductor substrate, a second conductivity type first semiconductor region formed on said semiconductor substrate which is isolated from said semiconductor substrate through p-n junction isolation, and a conductive layer extending above said first semiconductor region across an end portion of said first semiconductor region, a structure for preventing field concentration caused in said end portion of said first semiconductor region, existing under said conductive layer, through influence exerted by an electric field from said conductive layer, comprising: an insulating film formed on said end portion of said first semiconductor region between said first semiconductor region and said conductive layer; at least one conductive plate each having a first and second end portion and being formed in said insulating film in a manner that said at least one conductor plate is fully surrounded by said insulating film so as to be in a fully electrically floating state; and at least two first conductivity type first semiconductor floating diffusion regions formed in a surface of said end portion of said first semiconductor region to be alternately arranged with said conductive plate so that said first end portion of said at least one conductive plate overlaps with one of said at least two first conductivity type first semiconductor floating diffusion regions and said second end portion of said at least one conductive plate overlaps with another one of said at least two first conductivity type first semiconductor floating diffusion regions through said insulating film.
Claim 2
Dependent Claim 250 words
In a semiconductor device comprising a first conductivity type semiconductor substrate, a second conductivity type first semiconductor region formed on said semiconductor substrate which is isolated from said semiconductor substrate through p-n junction isolation, and a conductive layer extending above said first semiconductor region across an end portion of said first semiconductor region, a structure for preventing field concentration caused in said end portion of said first semiconductor region, existing under said conductive layer, through influence exerted by an electric field from said conductive layer, comprising: an insulating film formed on said end portion of said first semiconductor region between said first semiconductor region and said conductive layer; at least one conductive plate each having a first and second end portion and being formed in said insulating film in a manner that said at least one conductor plate is fully surrounded by said insulating film so as to be in a fully electrically floating state; and at least two first conductivity type first semiconductor floating diffusion regions formed in a surface of said end portion of said first semiconductor region to be alternately arranged with said conductive plate so that said first end portion of said at least one conductive plate overlaps with one of said at least two first conductivity type first semiconductor floating diffusion regions and said second end portion of said at least one conductive plate overlaps with another one of said at least two first conductivity type first semiconductor floating diffusion regions through said insulating film.
Claim 3
Dependent Claim 54 words
A structure in accordance with claim 1, wherein said first semiconductor region includes a portion of an epitaxial layer grown on said semiconductor substrate, which is isolated by a first conductivity type first isolating diffusion region formed in said epitaxial layer to extend from a surface of said epitaxial layer to said semiconductor substrate.
Claim 4
Dependent Claim 99 words
A structure in accordance with claim 2, wherein said semiconductor device further comprises a second conductivity type buried layer of an impurity concentration larger than that of said first semiconductor region, formed in a center of a boundary between said semiconductor substrate and said first semiconductor region, and a second conductivity type second diffusion region of an impurity concentration larger than that of said first semiconductor region formed in said first semiconductor region, which extends from a surface of said first semiconductor region to said buried layer and encloses portion of said first semiconductor region on said buried layer.
Claim 5
Dependent Claim 20 words
A structure in accordance with claim 3, wherein said at least one conductive plate includes a plurality of conductive plates.
Claim 6
Dependent Claim 51 words
A structure in accordance with claim 4, wherein capacitances of capacitive coupling of said conductive plates and said first semiconductor floating diffusion regions are so set that voltage potentials of said conductive plates and said first semiconductor floating diffusion regions substantially linearly change from a low level to a high level.
Claim 7
Dependent Claim 75 words
A structure in accordance with claim 3, further comprising: a first end conductive plate formed in said insulating film in arrangement with and adjacent to the alternate arrangement of said at least one conductive plate and said at least two first semiconductor floating diffusion regions, having one end portion electrically connected with said first isolating diffusion region and another end portion overlapping with one of said first semiconductor floating diffusion regions through said insulating film.
Claim 8
Dependent Claim 65 words
A structure in accordance with claim 6, further comprising: a second end conductive plate formed in said insulating film in arrangement with and adjacent to said alternative arrangement opposite to said first end conductive plate, having one end portion electrically connected with said second diffusion region and another end portion overlapping with another one of said first semiconductor floating diffusion regions through said insulating film.

References Cited (Backward Citations)

CH495629A Cited
US4567502A Cited
EP0095755A2 Cited
US4707719A Cited
US4801995A Cited
US4789886A Cited
DE3721001A1 Cited
US5043781A Cited
US5075739A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-04-19 1996-10-19 1997-04-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-04-19 2000-10-19 2001-04-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-04-19 2004-10-19 2005-04-20 $7700.00 Window Closed / Lapsed

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