US4567502A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planar type semiconductor device with a high breakdown voltage
Assignee: Toshiba Corp
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Filing: 1984-03-14
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Granted: 1986-01-28
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Expires: 2004-03-14
Abstract
Abstract A planar type semiconductor device having a high breakdown voltage, including a diffusion region of a P type formed in a semiconductor layer of an N type, a guard ring region of the P type formed in the semiconductor layer and surrounding the diffusion layer, and an insulating film covering the surface of the semiconductor layer between the diffusion and guard ring region. A field plate is provided which is kept at a potential equal to that of the diffusion region. The field plate covers the entire surface of that portion of the insulating film which is between the diffusion and guard ring regions.
Inventors
- 👤 Akio Nakagawa
- 👤 Tadashi Utagawa
- 👤 Tsuneo Tsukakoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:20
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D64/112; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D8/00; H10D8/411
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
196 words
A planar type semiconductor device having a high breakdown voltage, including: a diffusion region of a second conductivity type formed in a selected surface portion of a semiconductor layer of a first conductivity type; at least a first guard ring region of the second conductivity type formed in another surface portion of said semiconductor layer surrounding said diffusion region at a given distance; an insulating film covering a given portion of the surface of said semiconductor layer; a first conductive layer provided on that portion of said insulating film formed on the surface of said semiconductor layer between said diffusion region and said guard ring region, said first conductive layer kept at a potential equal to that of said diffusion region and covering the entire surface of that portion of said insulating film which is between said diffusion region and said guard ring region; and a second conductive layer provided on that portion of said insulating film formed on the surface of said semiconductor layer surrounding the first guard ring region, said second conductive layer kept at a potential equal to that of said first guard ring region and away from said diffusion region extending outwardly.
Claim 2
Dependent Claim
196 words
A planar type semiconductor device having a high breakdown voltage, including: a diffusion region of a second conductivity type formed in a selected surface portion of a semiconductor layer of a first conductivity type; at least a first guard ring region of the second conductivity type formed in another surface portion of said semiconductor layer surrounding said diffusion region at a given distance; an insulating film covering a given portion of the surface of said semiconductor layer; a first conductive layer provided on that portion of said insulating film formed on the surface of said semiconductor layer between said diffusion region and said guard ring region, said first conductive layer kept at a potential equal to that of said diffusion region and covering the entire surface of that portion of said insulating film which is between said diffusion region and said guard ring region; and a second conductive layer provided on that portion of said insulating film formed on the surface of said semiconductor layer surrounding the first guard ring region, said second conductive layer kept at a potential equal to that of said first guard ring region and away from said diffusion region extending outwardly.
Claim 3
Dependent Claim
87 words
A planar type semiconductor device as claimed in claim 1, comprising: a second guard ring region of the second conductivity type surrounding said first guard ring region at a given distance; said insulating film surrounding said first guard ring region formed on the surface portion of said semiconductor layer between said first and second guard ring regions; and said second conductive layer provided such that it covers the entire surface of that portion of said insulating film which is between said first and second guard ring regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-27 | 1989-07-29 | 1990-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-27 | 1993-07-29 | 1994-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-27 | 1997-07-29 | 1998-01-28 | $7700.00 | Window Closed / Lapsed |