US5200651A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Collector dot and circuit
Assignee: Sony Corp
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Filing: 1991-11-15
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Granted: 1993-04-06
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Expires: 2011-11-15
Abstract
Abstract A multi-output collector dot AND circuit wherein a logical AND signal can be formed from a pair of adjacent circuits and another logical AND circuit can also be formed from a pair of circuits spaced from each other. The collector dot AND circuit comprises a plurality of output transistors which are cascade connected to an output electrode of one of a pair of transistors constituting a differential circuit so that an output or outputs different from an output which is used to obtain a logical AND signal together with an output of an adjacent differential circuit are obtained from the one transistor. A number of dummy transistors equal to the number of the output transistors are cascade connected to an output electrode of the other transistor. Further, a constant-current source is connected to the differential circuit such that an electric current which flows from each of the output transistors connected to the one transistor is made equal in magnitude to an electric current which flows from a transistor of the adjacent differential circuit.
Inventors
- 👤 Yoshihiro Komatsu
- 👤 Masato Kawata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
230 words
A collector dot AND circuit, comprising: a first differential circuit including first and second transistors differentially connected to each other: a first output transistor connected to an output electrode of said first transistor; a second output transistor connected to an output electrode of said second transistor: a second differential circuit including third and fourth transistors differentially connected to each other: a predetermined plural number of third output transistors cascade connected to an output electrode of said third transistor for dividing an electric current outputted from said third transistor into electric currents of the predetermined plural number, an output terminal of one of said third output transistors being connected to an output terminal of said second output transistor so as to provide an AND output signal: a same predetermined plural number of dummy transistors connected between an output electrode of said fourth transistor and a power source for causing an electric current having an equal magnitude to that of an electric current flowing through said third transistor to flow through said fourth transistor: a first constant-current source for supplying a constant electric current to said first differential circuit: and a second constant-current source for supplying a constant electric current to said second differential circuit so that an electric current outputted from each of said third output transistors is equal in magnitude to an electric current outputted from said first output transistor.
Claim 2
Dependent Claim
230 words
A collector dot AND circuit, comprising: a first differential circuit including first and second transistors differentially connected to each other: a first output transistor connected to an output electrode of said first transistor; a second output transistor connected to an output electrode of said second transistor: a second differential circuit including third and fourth transistors differentially connected to each other: a predetermined plural number of third output transistors cascade connected to an output electrode of said third transistor for dividing an electric current outputted from said third transistor into electric currents of the predetermined plural number, an output terminal of one of said third output transistors being connected to an output terminal of said second output transistor so as to provide an AND output signal: a same predetermined plural number of dummy transistors connected between an output electrode of said fourth transistor and a power source for causing an electric current having an equal magnitude to that of an electric current flowing through said third transistor to flow through said fourth transistor: a first constant-current source for supplying a constant electric current to said first differential circuit: and a second constant-current source for supplying a constant electric current to said second differential circuit so that an electric current outputted from each of said third output transistors is equal in magnitude to an electric current outputted from said first output transistor.
Claim 3
Dependent Claim
31 words
A collector dot AND circuit according to claim 1, wherein one of said dummy transistors serves as an output transistor which provides another AND output signal together with another differential circuit.
Claim 4
Dependent Claim
166 words
A collector dot AND circuit according to claim 1, further comprising a third differential circuit including fifth and sixth transistors differentially connected to each other, a same predetermined plural number of fourth output transistors cascade connected to an output terminal of said fifth transistor, a same predetermined plural number of second dummy transistors connected between an output terminal of said sixth transistor and said power source for causing an electric current having an equal magnitude to that of an electric current flowing through said fifth transistor to flow through said sixth transistor, an output terminal of one of said third output transistors being connected to an output terminal of one of said second dummy transistors so as to provide another AND output signal, and a third constant-current source for supplying a constant electric current to said third differential circuit so that an electric current outputted from each of said fourth output transistors is equal in magnitude to an electric current outputted from said first output transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-05 | 1996-10-05 | 1997-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-05 | 2000-10-05 | 2001-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-05 | 2004-10-05 | 2005-04-06 | $7700.00 | Window Closed / Lapsed |