US4868420A
Expired / Lapsed
US
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Flip-flop circuit
Assignee: Hitachi Ltd
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Filing: 1988-11-18
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Granted: 1989-09-19
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Expires: 2008-11-18
Abstract
Abstract An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to α rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as α rays and does not cause soft errors.
Inventors
- 👤 Hiroyuki Itoh
- 👤 Masayoshi Yagyu
- 👤 Toshio Yamada
- 👤 Masaru Osanai
- 👤 Akira Masaki
- 👤 Mitsuo Usami
- 👤 Tohru Kobayashi
- 👤 Masato Hamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:06
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
195 words
A flip-flop circuit comprising: a first logic means having a first gate for receiving a first input signal and a second gate for receiving a second input signal; a second logic means having a third gate for receiving said first input signal and a fourth gate for receiving said second input signal; and a third logic means having a fifth gate having inputs coupled to outputs of said first and third gates and having an output coupled to inputs of said second and fourth gates, said third logic means further including a sixth gate having inputs coupled to outputs of said second and fourth gates and having an output coupled to inputs of said first and third gates, so that said fifth gate provides a first feedback path from the outputs of said first and third gates to the inputs of said second and fourth gates and said sixth gate provides a second feedback path from the output of said second and fourth gates to the inputs of said first and third gates, wherein said first and second feedback paths serve to reduce the generation of soft error in the operation of said flip-flop circuit.
Claim 2
Dependent Claim
195 words
A flip-flop circuit comprising: a first logic means having a first gate for receiving a first input signal and a second gate for receiving a second input signal; a second logic means having a third gate for receiving said first input signal and a fourth gate for receiving said second input signal; and a third logic means having a fifth gate having inputs coupled to outputs of said first and third gates and having an output coupled to inputs of said second and fourth gates, said third logic means further including a sixth gate having inputs coupled to outputs of said second and fourth gates and having an output coupled to inputs of said first and third gates, so that said fifth gate provides a first feedback path from the outputs of said first and third gates to the inputs of said second and fourth gates and said sixth gate provides a second feedback path from the output of said second and fourth gates to the inputs of said first and third gates, wherein said first and second feedback paths serve to reduce the generation of soft error in the operation of said flip-flop circuit.
Claim 3
Dependent Claim
201 words
A flip-flop circuit comprising: first logic means for receiving a first input signal and a feedback signal at first and second inputs thereof, respectively, and for providing a first logic signal at an output thereof in response to the first input signal and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means having inputs coupled to the first and second inputs of said first logic means, respectively, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs coupled to the outputs of said first and second logic means; fourth logic means having an input for receiving a second input signal and an input coupled to the output of said third logic means; and a feedback loop comprising said first, second, third and fourth logic means by feeding an output signal of said fourth logic means back to the second input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 4
Dependent Claim
201 words
A flip-flop circuit comprising: first logic means for receiving a first input signal and a feedback signal at first and second inputs thereof, respectively, and for providing a first logic signal at an output thereof in response to the first input signal and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means having inputs coupled to the first and second inputs of said first logic means, respectively, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs coupled to the outputs of said first and second logic means; fourth logic means having an input for receiving a second input signal and an input coupled to the output of said third logic means; and a feedback loop comprising said first, second, third and fourth logic means by feeding an output signal of said fourth logic means back to the second input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 5
Dependent Claim
71 words
A flip-flop circuit according to claim 2, further comprising: fifth logic means which has inputs for receiving the second signal and the output signal of said third logic means respectively; and sixth logic means having inputs coupled to outputs of said fourth and fifth logic means, wherein an output signal of said sixth logic means is fed back to the second input of said first logic means as the feedback signal.
Claim 6
Dependent Claim
25 words
A flip-flop circuit according to claim 2, wherein said third logic means is combined with said fourth logic means as a single three-input logic means.
Claim 7
Dependent Claim
31 words
A flip-flop circuit according to claim 4, wherein said third logic means is comprised of an OR gate which receives the first and second logic signals and the second input signal.
Claim 8
Dependent Claim
21 words
A flip-flop circuit according to claim 5, wherein said second logic means is comprised of a NAND gate and an inverter.
Claim 9
Dependent Claim
73 words
A flip-flop circuit according to claim 2, wherein said first logic means has a transistor circuit which is comprised of two or more transistors having emitters connected together and which receive at least the first input signal and the feedback signal through bases thereof, and wherein the first logic signal is obtained from collectors of the transistors that are provided with the first input signal and the feedback signal through the bases thereof.
Claim 10
Dependent Claim
82 words
A flip-flop circuit according to claim 7, wherein said fourth logic means has a transistor circuit which is comprised of two or more transistors having emitters connected together and which receive at least the second input signal and the output signal of said third logic means through bases thereof, and wherein the feedback signal is obtained from collectors of the transistors that are provided with the second input signal and the output signal of said third logic means through the bases thereof.
Claim 11
Dependent Claim
207 words
A flip-flop circuit comprising: first logic means for receiving a first input signal and a feedback signal at first and second inputs thereof, respectively, and for providing first and third logic signals having opposite phase at outputs thereof, respectively, in response to the first input signal and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means which has an input for receiving the third logic signal, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs for receiving the first logic signal of said first and second logic signals of said second logic means; fourth logic means having an input for receiving a second input signal and an input coupled to the output of said third logic means; and a feedback loop comprising said first, second, third and fourth logic means by feeding an output signal of said fourth logic means back to the second input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 12
Dependent Claim
207 words
A flip-flop circuit comprising: first logic means for receiving a first input signal and a feedback signal at first and second inputs thereof, respectively, and for providing first and third logic signals having opposite phase at outputs thereof, respectively, in response to the first input signal and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means which has an input for receiving the third logic signal, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs for receiving the first logic signal of said first and second logic signals of said second logic means; fourth logic means having an input for receiving a second input signal and an input coupled to the output of said third logic means; and a feedback loop comprising said first, second, third and fourth logic means by feeding an output signal of said fourth logic means back to the second input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 13
Dependent Claim
25 words
A flip-flop circuit according to claim 9, wherein said third logic means is combined with said fourth logic means as a single three-input logic means.
Claim 14
Dependent Claim
55 words
A flip-flop circuit according to claim 9, wherein said first logic means further comprises an inverter for receiving the second input signal and a logic gate having inputs for receiving the first input signal and output signal of said inverter and which produces an output signal to the first input of said first logic means.
Claim 15
Dependent Claim
189 words
A flip-flop circuit comprising: first logic means for receiving first and second input signals and a feedback signal at first, second and third inputs thereof, respectively, and for providing first and third logic signals having opposite phase at outputs thereof, respectively, in response to the first and second input signals and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means which has an input for receiving the third logic signal, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs for receiving the first logic signal of said first logic means and the second logic signal of said second logic means; and a feedback loop comprising said first, second and third logic means by feeding an output signal of said third logic means back to the third input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 16
Dependent Claim
189 words
A flip-flop circuit comprising: first logic means for receiving first and second input signals and a feedback signal at first, second and third inputs thereof, respectively, and for providing first and third logic signals having opposite phase at outputs thereof, respectively, in response to the first and second input signals and the feedback signal, wherein the logical level of the first logic signal can be changed to another logical level by soft errors; second logic means which has an input for receiving the third logic signal, and which produces a second logic signal having the same logic level as the first logic signal; third logic means having inputs for receiving the first logic signal of said first logic means and the second logic signal of said second logic means; and a feedback loop comprising said first, second and third logic means by feeding an output signal of said third logic means back to the third input of said first logic means as the feedback signal, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first and second input signals.
Claim 17
Dependent Claim
25 words
A flip-flop circuit according to claim 12, wherein said third logic means is combined with said first logic means as a single three-input logic means.
Claim 18
Dependent Claim
98 words
A flip-flop circuit according to claim 12, wherein said first logic means is comprised of an inverter for receiving the second input signal, a first logic gate having inputs for receiving the first input signal and output signal of said inverter, a second logic gate having inputs for receiving the first input signal and the feedback signal, a third logic gate having inputs for receiving the second input signal and the feedback signal, and a fourth logic gate which receives output signals of said first, second and third gates and which produces the first and third logic signals.
Claim 19
Dependent Claim
154 words
A flip-flop circuit according to claim 12, wherein said first logic means has two or more transistor circuits each comprised of two or more transistors having emitters connected together and which receive one of the input signals and the feedback signal and a reference signal through bases thereof, wherein a logic signal which is obtained from a collector of the transistor that is provided with the reference signal through the base thereof is input to an AND gate in each of said transistor circuits, and wherein a logic signal which is obtained from collectors of the transistors that are provided with the first input signal and the feedback signal through the bases thereof is input to an OR gate in each of said transistor circuits, and wherein the output of said AND gate is used as the first logic signal and the output of said OR gate is used as the third logic signal.
Claim 20
Dependent Claim
17 words
A flip-flop circuit according to claim 15, wherein said second logic means is comprised of an inverter.
Claim 21
Dependent Claim
36 words
A flip-flop circuit according to claim 15, wherein said second logic means is comprised of a differential circuit which receives the first logic signal and the third logic signal, and which produces the second logic signal.
Claim 22
Dependent Claim
96 words
A flip-flop circuit according to claim 12, wherein said first logic means has two or more transistor circuits each comprised of two transistors having emitters connected together and which receive one of the input and feedback signals and a reference signal through bases thereof, wherein the first logic signal is obtained from a collector of the transistor that is provided with the reference signal through the base thereof, and the third logic signal is obtained from a collector of the transistor that is provided with one of the input and feedback signals through the base thereof.
Claim 23
Dependent Claim
36 words
A flip-flop circuit according to claim 18, wherein said second logic means is comprised of a differential circuit which receives the first logic signal and the third logic signal, and which produces the second logic signal.
Claim 24
Dependent Claim
35 words
A flip-flop circuit according to claim 18, wherein said third logic means is comprised of first and second emitter-follower transistors which receive the first logic signal and the third logic signal at bases thereof, respectively.
Claim 25
Dependent Claim
57 words
A flip-flop circuit according to claim 20, wherein said second logic means is comprised of a differential circuit which receives the first logic signal and the third logic signal, and which produces an out-of-phase output signal to the emitter of said first emitter-follower transistors and an in-phase output signal in the emitter of said second emitter-follower transistor.
Claim 26
Dependent Claim
288 words
A flip-flop circuit comprising: first logic means having a first transistor circuit for receiving at least a first input signal at a first input and for providing first and third logic signals having opposite phase at first and second output nodes thereof, respectively, said first transistor circuit having two or more transistors, emitters of which are coupled to each other, one of the bases of which is coupled to the first input, one of the collectors of which is coupled to the first output node, and the other of the collectors of which is coupled to the second output node; second logic means having a second transistor circuit which receives the third logic signal and which produces a third logic signal having the same logic level as the first logic signal; and third logic means having a first emitter-follower transistor, a base of which is coupled to the first output node for receiving the first logic signal, and an emitter of which is coupled to an output of said second transistor circuit, said first logic means having a third transistor circuit for receiving an output signal of said third logic means as a feedback signal, said third transistor circuit having two transistors, emitters of which are coupled to each other, one of the bases of which is coupled to the emitter of said first emitter-follower transistor, one of the collectors of which is coupled to the first output node, and the other of the collectors of which is coupled to the second output node, wherein a feedback loop comprises said first, second and third logic means, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first input signal.
Claim 27
Dependent Claim
288 words
A flip-flop circuit comprising: first logic means having a first transistor circuit for receiving at least a first input signal at a first input and for providing first and third logic signals having opposite phase at first and second output nodes thereof, respectively, said first transistor circuit having two or more transistors, emitters of which are coupled to each other, one of the bases of which is coupled to the first input, one of the collectors of which is coupled to the first output node, and the other of the collectors of which is coupled to the second output node; second logic means having a second transistor circuit which receives the third logic signal and which produces a third logic signal having the same logic level as the first logic signal; and third logic means having a first emitter-follower transistor, a base of which is coupled to the first output node for receiving the first logic signal, and an emitter of which is coupled to an output of said second transistor circuit, said first logic means having a third transistor circuit for receiving an output signal of said third logic means as a feedback signal, said third transistor circuit having two transistors, emitters of which are coupled to each other, one of the bases of which is coupled to the emitter of said first emitter-follower transistor, one of the collectors of which is coupled to the first output node, and the other of the collectors of which is coupled to the second output node, wherein a feedback loop comprises said first, second and third logic means, the feedback loop having either one of two stable states, wherein the stable state can be changed by the first input signal.
Claim 28
Dependent Claim
81 words
A flip-flop circuit according to claim 22, wherein said first logic means further comprises a fourth transistor circuit for receiving a second input signal, said fourth transistor circuit having two transistors, emitters of which are coupled to each other, one of the bases of which receives the second input signal, and collectors of which are coupled to the emitters of said first and third transistor circuits respectively, wherein the stable state can be changed by the first and second input signals.
Claim 29
Dependent Claim
30 words
A flip-flop circuit according to claim 22, wherein said second transistor circuit has an emitter-follower transistor, an emitter of which is coupled to the emitter of the first emitter-follower transistor.
Claim 30
Dependent Claim
16 words
A flip-flop circuit according to claim 22, wherein said second transistor circuit has an inverter circuit.
Claim 31
Dependent Claim
35 words
A flip-flop circuit according to claim 25, wherein said inverter circuit is comprised of a differential circuit, inputs of which are coupled to the first and second output nodes of said first transistor circuit, respectively.
Claim 32
Dependent Claim
51 words
A flip-flop circuit according to claim 23, wherein said third logic means further has a second emitter-follower transistor, a base of which is coupled to the second output node for receiving the third logic signal, and an emitter of which is coupled to the other base of said third transistor circuit.
Claim 33
Dependent Claim
67 words
A flip-flop circuit according to claim 27, wherein said second transistor circuit is comprised of a differential circuit, inputs of which are coupled to the first and second output nodes of said first transistor circuit, respectively, an out-of-phase output of which is coupled to the emitter of said first emitter-follower transistor and an in-phase output of which is coupled to the emitter of said second emitter-follower transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |