Patent US5196787A successfully refreshed from Google Patents.
US5196787A
Expired / Lapsed
US
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Test circuit for screening parts
Assignee: Texas Instruments Inc
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Filing: 1992-07-23
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Granted: 1993-03-23
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Expires: 2012-07-23
Abstract
Abstract A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.
Inventors
- 👤 Kevin M. Ovens
- 👤 Jeffrey A. Niehaus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:08
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2882
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
124 words
Circuitry for testing an integrated circuit, comprising: model circuitry on the integrated circuit having a plurality of transistors with a size ratio proportional to the minimum desired beta characteristic of the transistors on the integrated circuit, coupled so that the current drawn by said transistors is proportional to said size ratio of said transistors; a test node coupled to a pin of said integrated circuit and said model circuitry; and operable such that an accurate estimate of the performance of the transistors on said integrated circuit may be obtained by observing the current drawn by said transistors within said model circuitry in response to certain voltages applied at said test node, such observations being made without enabling the other circuitry on said integrated circuit.
Claim 2
Dependent Claim
124 words
Circuitry for testing an integrated circuit, comprising: model circuitry on the integrated circuit having a plurality of transistors with a size ratio proportional to the minimum desired beta characteristic of the transistors on the integrated circuit, coupled so that the current drawn by said transistors is proportional to said size ratio of said transistors; a test node coupled to a pin of said integrated circuit and said model circuitry; and operable such that an accurate estimate of the performance of the transistors on said integrated circuit may be obtained by observing the current drawn by said transistors within said model circuitry in response to certain voltages applied at said test node, such observations being made without enabling the other circuitry on said integrated circuit.
Claim 3
Dependent Claim
68 words
The model circuitry of claim 1 wherein said plurality of transistors comprises: a first transistor having an emitter, a base, and collector with said collector coupled to said test node and said emitter coupled to ground; and a second transistor having an emitter, a base, and a collector, with said collector and said base coupled to said base of said first transistor, and said emitter coupled to ground.
Claim 4
Dependent Claim
35 words
The circuitry of claim 1 wherein said model circuitry further comprises: a diode operable to draw current responsive to the forward bias voltage of said diode; and a test node coupled to said integrated circuit.
Claim 5
Dependent Claim
23 words
The circuitry of claim 2 wherein said first transistor is operable to draw current responsive to the beta value of said first transistor.
Claim 6
Dependent Claim
27 words
The circuitry of claim 3 wherein said model circuitry further comprises a resistor coupled between the anode of said diode and the base of said first transistor.
Claim 7
Dependent Claim
21 words
The circuitry of claim 3 wherein said resistor is operable to draw current responsive to the resistive value of said resistor.
Claim 8
Dependent Claim
33 words
The circuitry of claim 1 and further comprising: a voltage source associated with the integrated circuit circuitry to disable said model circuitry responsive to said voltage source being at a first voltage level.
Claim 9
Dependent Claim
22 words
The circuitry of claim 1 further comprising: circuitry for enabling the model circuitry responsive to a predetermined signal on said test node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |