Patent US5196363A successfully refreshed from Google Patents.
US5196363A
Expired / Lapsed
US
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Method of forming mist type dynamic random access memory cell
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-12-28
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Granted: 1993-03-23
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Expires: 2010-12-28
Abstract
Abstract A dynamic random access memory cell having a mixed trenched stacked capacitor, and a formation process thereof are disclosed. According to the present invention, the punch-through phenomenon is prevented by providing a difference between the trench depths of the trenched capacitors. Further, the insufficient capacitance of the capacitor having a shallower trench is compensated by making the area of the electrode of the stacked capacitor larger than the area of the electrode of the stacked capacitor of the memory cell having a deeper trenched capacitor. Thus, the coupling phenomenon liable to occur between the stacked capacitors can be prevented, thereby providing a DRAM cell applicable to ultra large scale integrated circuit.
Inventors
- 👤 Youngtae Kang
- 👤 Laeku Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:11
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10B12/377; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
128 words
A process for making a dynamic random access memory cell structure with at least two memory cells having a shallow first trenched capacitor and a deeper second trenched capacitor comprising: forming a shallow first trench using a first mask; forming a second trench deeper than said first shallow trench using a second mask; applying a conductive layer to serve as storage electrodes of the capacitors onto said first and second trenches so that a portion of the conductive layer is on each of the first and second trenches and covering said conductive layer with a third mask; and etching said conductive layer to form the storage electrodes, wherein the storage electrode on the shallow trench having a larger surface area than the storage electrode on the deep trench.
Claim 2
Dependent Claim
128 words
A process for making a dynamic random access memory cell structure with at least two memory cells having a shallow first trenched capacitor and a deeper second trenched capacitor comprising: forming a shallow first trench using a first mask; forming a second trench deeper than said first shallow trench using a second mask; applying a conductive layer to serve as storage electrodes of the capacitors onto said first and second trenches so that a portion of the conductive layer is on each of the first and second trenches and covering said conductive layer with a third mask; and etching said conductive layer to form the storage electrodes, wherein the storage electrode on the shallow trench having a larger surface area than the storage electrode on the deep trench.
Claim 3
Dependent Claim
64 words
A process according to claim 1 further comprising forming said structure with at least two adjacent memory cells with a capacitor, the area of the storage electrode of said capacitor of one memory cell having the shallow first trenched capacitor being larger than the area of the second storage electrode of said capacitor of an adjacent memory cell having the deeper second trenched capacitor.
Claim 4
Dependent Claim
18 words
A process according to claim 2 wherein an area including two adjacent memory cells comprises an active region.
Claim 5
Dependent Claim
37 words
A process according to claim 3 wherein said first and second trenches are formed in a single etching step by providing a structure with trenches of difference depth in advance on the portion of the active region.
References Cited (Backward Citations)
JPS57204144A
Cited
US5011788A
Cited
US4860071A
Cited
JPS61225863A
Cited
JPS62123764A
Cited
JPS62179759A
Cited
JPS63239969A
Cited
JPS63284850A
Cited
US4912535A
Cited
US4951175A
Cited
JPH0281472A
Cited
JPH02106958A
Cited
JPH02116160A
Cited
US5077232A
Cited
US5066608A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |