Method of manufacturing InP junction FETS and junction HEMTS using dual implantation and double nitride layers

Claim 1

A method of fabricating a sub-micron gate semiconductor device which device includes source, drain, gate regions and a channel region connecting the source and drain regions, which method comprises the steps of: epitaxially growing a sample with the layered sequence of a semi-insulating InP substrate, a channel region, an n - doped InP etch buffer layer and a p + doped InGaAs cap layer; growing a first insulating film on top of said layered sample; patterning said first insulating film for aiding the selective, etch registration of n + implants into said source and drain regions; forming n + source and drain regions by the selective implantation of an n-type dopant, while using said first insulating layer as a mask; applying a second insulating layer on said first insulating layer; applying a photoresist layer and delineating a gate photoresist opening above said second insulating layer; patterning said first and second insulating layers by anisotropic etching to limit the amount of undercutting while using the photoresist layer as a mask; sequentially implanting a first ion selected from a group consisting of P and As, followed by the implantation of a second ion selected from the group consisting of Be, Zn, and Cadmium through the gate opening into the gate region down to the channel region; annealing the structure with said first and second insulating layers still in place; patterning a gate metallization using said gate photoresist opening for gate registration and self-alignment; defining source and drain metalizations on top of the n + implant regions on either side of the gate; and removing the remaining p + InGaAs on either side of the gate.

Claim 2

A method of fabricating a sub-micron gate semiconductor device which device includes source, drain, gate regions and a channel region connecting the source and drain regions, which method comprises the steps of: epitaxially growing a sample with the layered sequence of a semi-insulating InP substrate, a channel region, an n - doped InP etch buffer layer and a p + doped InGaAs cap layer; growing a first insulating film on top of said layered sample; patterning said first insulating film for aiding the selective, etch registration of n + implants into said source and drain regions; forming n + source and drain regions by the selective implantation of an n-type dopant, while using said first insulating layer as a mask; applying a second insulating layer on said first insulating layer; applying a photoresist layer and delineating a gate photoresist opening above said second insulating layer; patterning said first and second insulating layers by anisotropic etching to limit the amount of undercutting while using the photoresist layer as a mask; sequentially implanting a first ion selected from a group consisting of P and As, followed by the implantation of a second ion selected from the group consisting of Be, Zn, and Cadmium through the gate opening into the gate region down to the channel region; annealing the structure with said first and second insulating layers still in place; patterning a gate metallization using said gate photoresist opening for gate registration and self-alignment; defining source and drain metalizations on top of the n + implant regions on either side of the gate; and removing the remaining p + InGaAs on either side of the gate.

Claim 15

A method of fabricating a sub-micron gate semiconductor device which device includes source, drain, gate regions and a channel region connecting the source and drain regions, which method comprises the steps of: growing a first insulating layer on a semiconductor structure including a semi-insulating substrate and a channel region; delineating source and drain regions through said first insulating layer and implanting source and drain regions into said semi-insulating substrate; growing a second insulating layer on said first insulating layer; applying a photoresist layer and delineating a gate photoresist opening above said second insulating layer; patterning said first and second insulating layers by anisotropic etching to limit the amount of undercutting while using the photoresist layer as a mask; sequentially implanting a first ion selected from a group consisting of P and As, followed by the implantation of a second ion selected from the group consisting of Be, Zn, and Cadmium through the gate opening into the gate region down to the channel region; annealing the structure with said first and second insulating layers still in place; patterning a gate metallization; and defining source and drain metalizations.

Claim 16

A method of fabricating a sub-micron gate semiconductor device which device includes source, drain, gate regions and a channel region connecting the source and drain regions, which method comprises the steps of: growing a first insulating layer on a semiconductor structure including a semi-insulating substrate and a channel region; delineating source and drain regions through said first insulating layer and implanting source and drain regions into said semi-insulating substrate; growing a second insulating layer on said first insulating layer; applying a photoresist layer and delineating a gate photoresist opening above said second insulating layer; patterning said first and second insulating layers by anisotropic etching to limit the amount of undercutting while using the photoresist layer as a mask; sequentially implanting a first ion selected from a group consisting of P and As, followed by the implantation of a second ion selected from the group consisting of Be, Zn, and Cadmium through the gate opening into the gate region down to the channel region; annealing the structure with said first and second insulating layers still in place; patterning a gate metallization; and defining source and drain metalizations.