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Method of manufacturing semiconductor device

Assignee: Canon Inc
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Filing: 1991-08-19
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Granted: 1993-02-23
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Expires: 2011-08-19
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Abstract

Abstract A method of manufacturing a semiconductor device having a photoconductive semiconductor layer formed on a substrate and a pair of electrodes formed on the semiconductor layer with an ohmic contact layer interposed therebetween, wherein the ohmic contact layer is removed after the etching process of the semiconductor layer.

Inventors

  • 👤 Chiori Mochizuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 18:21
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10F; H10F30/00; H10F30/10; H10F30/15; H10F39/00; H10F39/10; H10F39/12; H10F39/191; H10F71/00; H10F71/10; H10F71/103; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02P; Y02P70/00; Y02P70/50; Y10; Y10S; Y10S148/00; Y10S148/105

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 134 words
A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a semiconductor region and a pair of electrodes disposed on said semiconductor region through an ohmic contact region disposed on said semiconductor region, comprising the sequential steps of: forming a semiconductor layer on said substrate, an ohmic contact layer on said semiconductor layer, and a conductive layer on said ohmic contact layer; removing a portion of said conductive layer, whereby said pair of electrodes are formed on said ohmic contact layer; removing a portion of said semiconductor layer and said ohmic contact layer to isolate each of said plurality of semiconductor elements; removing a portion of said ohmic contact layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
Claim 2
Independent Claim 134 words
A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a semiconductor region and a pair of electrodes disposed on said semiconductor region through an ohmic contact region disposed on said semiconductor region, comprising the sequential steps of: forming a semiconductor layer on said substrate, an ohmic contact layer on said semiconductor layer, and a conductive layer on said ohmic contact layer; removing a portion of said conductive layer, whereby said pair of electrodes are formed on said ohmic contact layer; removing a portion of said semiconductor layer and said ohmic contact layer to isolate each of said plurality of semiconductor elements; removing a portion of said ohmic contact layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
Claim 3
Dependent Claim 24 words
A method of manufacturing a semiconductor device according to claim 1, wherein said ohmic contact layer is patterned using said electrodes as a mask.
Claim 4
Dependent Claim 21 words
A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer is made of amorphous silicon hydride.
Claim 5
Dependent Claim 28 words
A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer and/or said ohmic contact layer is removed by a reactive ion etching method.
Claim 6
Dependent Claim 18 words
A method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor element is a photosensor.
Claim 7
Dependent Claim 18 words
A method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor element is a transistor.
Claim 8
Independent Claim 146 words
A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a first semiconductor layer and a pair of electrodes disposed on said first semiconductor layer through a second semiconductor layer having a lower resistivity than said first semiconductor layer, comprising the sequential steps of: forming a first semiconductor layer on said substrate; forming a second semiconductor layer on said first semiconductor layer; and forming a conductive layer on said second semiconductor layer; removing a portion of said conductive layer, whereby said pair of electrodes are formed on said second semiconductor layer; removing a portion of said first semiconductor layer and said second semiconductor layer to isolate each of the plurality of semiconductor elements; and removing a portion of said second semiconductor layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
Claim 9
Independent Claim 146 words
A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a first semiconductor layer and a pair of electrodes disposed on said first semiconductor layer through a second semiconductor layer having a lower resistivity than said first semiconductor layer, comprising the sequential steps of: forming a first semiconductor layer on said substrate; forming a second semiconductor layer on said first semiconductor layer; and forming a conductive layer on said second semiconductor layer; removing a portion of said conductive layer, whereby said pair of electrodes are formed on said second semiconductor layer; removing a portion of said first semiconductor layer and said second semiconductor layer to isolate each of the plurality of semiconductor elements; and removing a portion of said second semiconductor layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
Claim 10
Dependent Claim 18 words
A method for manufacturing a semiconductor device according to claim 7, wherein said semiconductor element is a photosensor.
Claim 11
Dependent Claim 18 words
A method for manufacturing a semiconductor device according to claim 7, wherein said semiconductor element is a transistor.

References Cited (Backward Citations)

US4405915A Cited
JPS58190061A Cited
US4545111A Cited
US4581099A Cited
JPS61201461A Cited
US4931661A Cited
US4857751A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-02-23 1996-08-24 1997-02-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-02-23 2000-08-24 2001-02-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-02-23 2004-08-24 2005-02-23 $7700.00 Window Closed / Lapsed

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