Patent US5185879A successfully refreshed from Google Patents.
US5185879A
Expired / Lapsed
US
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Cache system and control method therefor
Assignee: Individual
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Filing: 1991-07-22
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Granted: 1993-02-09
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Expires: 2011-07-22
Abstract
Abstract A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the CPU and cache and the signal decided only by the CPU, or when at a cache miss, the cache gives the CPU a control signal requesting reexecution of memory access and a control signal to allow the memory system to accept memory access to thereby operate the cache dependently on the CPU, so that even when either the CPU or the cache is the bus master, signal transmit-receive with respect to the memory system is adapted to be carried out substantially at the same timing. Furthermore, where a cache miss occurs when the CPU accesses to single data, and in order to cope with the case that a plurality of data from the memory system to the cache are transferred, the data of address next to the accessed address by the CPU is initially transferred from the memory system to the CPU, thereafter data is transferred to the CPU while changing the address in a so-called round robin method, and at last the object data for the CPU is controlled to be transferred in parallel to the CPU and cache, thereby minimizing the number of times for data transfer from the memory system to the cache.
Inventors
- 👤 Akira Yamada
- 👤 Tatsuo Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:28
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0884
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
194 words
A cache system in which a CPU and a cache, each driven by a common timing clock and operative as a bus master, are connected through a system bus to a memory system, comprising: a first signal line comprising a first portion connected between said CPU and said cache, and a second portion connected to said system bus, for transmitting and receiving a common signal to and from whichever one of said CPU and said cache is operating as a bus master; a second signal line comprising a common portion connected to said system bus, a first portion connected to said CPU and a second portion connected to said cache, said first and second portions intermittently connected to said common portion; first means for placing said CPU in a standby state and connecting the common portion to the first portion of said second signal line between said system bus and said cache when said cache is operating as a bus master; and second means for connecting the common portion to the second portion of said second signal line between said system bus and said CPU when said CPU is operating as a bus master.
Claim 2
Dependent Claim
194 words
A cache system in which a CPU and a cache, each driven by a common timing clock and operative as a bus master, are connected through a system bus to a memory system, comprising: a first signal line comprising a first portion connected between said CPU and said cache, and a second portion connected to said system bus, for transmitting and receiving a common signal to and from whichever one of said CPU and said cache is operating as a bus master; a second signal line comprising a common portion connected to said system bus, a first portion connected to said CPU and a second portion connected to said cache, said first and second portions intermittently connected to said common portion; first means for placing said CPU in a standby state and connecting the common portion to the first portion of said second signal line between said system bus and said cache when said cache is operating as a bus master; and second means for connecting the common portion to the second portion of said second signal line between said system bus and said CPU when said CPU is operating as a bus master.
Claim 3
Dependent Claim
61 words
The system of claim 1, including means for detecting that object data for accessing is not stored in said cache during a memory access cycle controlled by said CPU and, in response, placing said CPU in a standby state, transferring object data from said memory system to said cache, and storing said object data transferred to said cache in said CPU.
Claim 4
Dependent Claim
22 words
The system of claim 1, wherein said first and second means include a multiplexer controlled by a signal generated by said cache.
Claim 5
Dependent Claim
113 words
A cache, comprising: a CPU, a cache and a memory system connected directly or indirectly to a common system bus, said CPU controlling memory access operations for accessing object data; means for detecting that object data to be accessed during a memory access operation controlled by said CPU is not stored in said cache; and means incorporated in said cache and responsive to a detection by said means for detecting for generating a first control signal requesting said CPU to re-execute a memory access operation of said memory system for said object data and a second control signal for requesting said memory system to accept said memory access operations requested by said CPU.
Claim 6
Dependent Claim
113 words
A cache, comprising: a CPU, a cache and a memory system connected directly or indirectly to a common system bus, said CPU controlling memory access operations for accessing object data; means for detecting that object data to be accessed during a memory access operation controlled by said CPU is not stored in said cache; and means incorporated in said cache and responsive to a detection by said means for detecting for generating a first control signal requesting said CPU to re-execute a memory access operation of said memory system for said object data and a second control signal for requesting said memory system to accept said memory access operations requested by said CPU.
Claim 7
Dependent Claim
218 words
A cache system, comprising: a CPU, a cache and a memory system each driven by a common timing clock and connected directly or indirectly to a system bus, each said CPU and cache being operable as a bus master, said CPU controlling memory access operations for accessing object data; a first signal line connected to said system bus, said CPU and said cache and transmitting and receiving signal to and from whichever one of said CPU and cache is operating as a bus master; a second signal line; means for selectively connecting said second signal line between said system bus and said CPU or between said system bus and said cache, wherein said second signal line carries a different signal depending on which one of said CPU and said cache is operating a bus master; means for detecting that object data to be accessed during a memory access operation controlled by said CPU is not stored in said cache; and means incorporated in said cache and responsive to a detection by said means for detecting for generating a first control signal requesting said CPU to re-execute a memory access operation of said memory system for said object data and a second control signal for requesting said memory system to accept said memory access operation requested by said CPU.
Claim 8
Dependent Claim
218 words
A cache system, comprising: a CPU, a cache and a memory system each driven by a common timing clock and connected directly or indirectly to a system bus, each said CPU and cache being operable as a bus master, said CPU controlling memory access operations for accessing object data; a first signal line connected to said system bus, said CPU and said cache and transmitting and receiving signal to and from whichever one of said CPU and cache is operating as a bus master; a second signal line; means for selectively connecting said second signal line between said system bus and said CPU or between said system bus and said cache, wherein said second signal line carries a different signal depending on which one of said CPU and said cache is operating a bus master; means for detecting that object data to be accessed during a memory access operation controlled by said CPU is not stored in said cache; and means incorporated in said cache and responsive to a detection by said means for detecting for generating a first control signal requesting said CPU to re-execute a memory access operation of said memory system for said object data and a second control signal for requesting said memory system to accept said memory access operation requested by said CPU.
Claim 9
Dependent Claim
23 words
A cache system of claim 5, wherein said means for selectively connecting comprises a multiplexer controlled by a signal generated by said cache.
Claim 10
Independent Claim
109 words
A method of controlling a cache system having a CPU, a cache and a memory system, comprising the steps of: controlling said CPU to access object data possibly stored in said cache; if said object data is not stored in said cache and a plurality of data is available to be block-transferred from said system memory to said cache, (a) first sequentially transferring, from said memory system and writing to said cache, remaining available data except for said object data while changing the block-address by one, and (b) then transferring said object data, from said memory system whereby said CPU and said cache accept said object data in parallel.
Claim 11
Independent Claim
109 words
A method of controlling a cache system having a CPU, a cache and a memory system, comprising the steps of: controlling said CPU to access object data possibly stored in said cache; if said object data is not stored in said cache and a plurality of data is available to be block-transferred from said system memory to said cache, (a) first sequentially transferring, from said memory system and writing to said cache, remaining available data except for said object data while changing the block-address by one, and (b) then transferring said object data, from said memory system whereby said CPU and said cache accept said object data in parallel.
Claim 12
Dependent Claim
17 words
The method of claim 7, wherein said block-address is incremented during said steps of (a) and (b).
Claim 13
Dependent Claim
18 words
The method of claim 7, wherein said block-address is decremented during said steps of first and sequentially transferring.
References Cited (Backward Citations)
US3993981A
Cited
US4030075A
Cited
US4195340A
Cited
US4214303A
Cited
US4323968A
Cited
US4323967A
Cited
US4433374A
Cited
US4661905A
Cited
US4646233A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-02-09 | 1996-08-10 | 1997-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-02-09 | 2000-08-10 | 2001-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-02-09 | 2004-08-10 | 2005-02-09 | $7700.00 | Window Closed / Lapsed |