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US5172341A
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Serial dram controller with multi generation interface
Assignee: Dallas Semiconductor Corp
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Filing: 1991-07-16
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Granted: 1992-12-15
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Expires: 2011-07-16
Abstract
Abstract A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.
Inventors
- 👤 Pravin T. Amin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/406
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
133 words
A dynamic memory controller, comprising: (a) a reset input terminal; (b) a clock input terminal; (c) a bidirectional serial terminal; (d) dynamic memory refresh control signal output terminals; (e) a bidirectional dynamic memory data port selectively coupled to said serial terminal; (f) a refresh time period selector, said selector accessed by joint signals on said reset, clock, and serial terminals; (g) refresh signal generating circuitry coupled to said clock input terminal and said refresh control signal output terminals, said circuitry generating refresh dynamic memory refresh signals at said output terminals for a refresh time period when a signal at said clock input terminal switches from a first state to a second state, said generating further refresh control signals at said output terminals when said signal at said clock remains in said second state.
Claim 2
Dependent Claim
133 words
A dynamic memory controller, comprising: (a) a reset input terminal; (b) a clock input terminal; (c) a bidirectional serial terminal; (d) dynamic memory refresh control signal output terminals; (e) a bidirectional dynamic memory data port selectively coupled to said serial terminal; (f) a refresh time period selector, said selector accessed by joint signals on said reset, clock, and serial terminals; (g) refresh signal generating circuitry coupled to said clock input terminal and said refresh control signal output terminals, said circuitry generating refresh dynamic memory refresh signals at said output terminals for a refresh time period when a signal at said clock input terminal switches from a first state to a second state, said generating further refresh control signals at said output terminals when said signal at said clock remains in said second state.
References Cited (Backward Citations)
US3737879A
Cited
US5033027A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |