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US5168499A
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Fault detection and bypass in a sequence information signal processor
Assignee: California Institute of Technology
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Filing: 1990-10-02
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Granted: 1992-12-01
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Expires: 2010-10-02
Abstract
Abstract The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.
Inventors
- 👤 John C. Peterson
- 👤 Edward T. Chow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2023; G06F11/2028; G06F11/2051; G06F17/00; G06F17/10; G06F7/00; G06F7/02; G06F11/2035; G06F11/2043; G06F11/22; G06F11/2205; G06F11/2236; G06F2201/00; G06F2201/83
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
116 words
In a systolic array of identical, serially interconnected processor elements, a fault detection circuit comprising: a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element; a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.
Claim 2
Dependent Claim
116 words
In a systolic array of identical, serially interconnected processor elements, a fault detection circuit comprising: a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element; a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.
Claim 3
Dependent Claim
99 words
The fault detection circuit recited in claim 1 further comprising: a plurality of two parallel-input multiplexers, one such multiplexer being connected between each adjacent pair of said processor elements, one of said multiplexer parallel inputs being connected to the immediately adjacent processor element and the other of said multiplexer parallel inputs being connected to the processor element immediately preceding said immediately adjacent processor element; and means for switching each said multiplexer between said respective parallel inputs depending upon whether the scan output signal of said immediately adjacent processor element is different or identical to the remaining scan output signals.
Claim 4
Dependent Claim
65 words
The fault detection circuit recited in claim 2 wherein said switching means comprises a switching signal terminal on each said multiplexer and a register for storing a plurality of switching signals, said switching signals being applied to respective ones of said switching signal terminals, the state of each such switching signal being controlled in accordance with the plurality of encoded signals generated by said encoder.
Claim 5
Dependent Claim
48 words
The fault detection circuit recited in claim 3 wherein said switching signals are also applied to said comparator and wherein said comparator comprises means for inhibiting said error signal after the multiplexer corresponding to a scan register which has generated a different scan output signal, has been switched.
Claim 6
Dependent Claim
44 words
The fault detection circuit recited in claim 1 further comprising: at least one, two parallel-input multiplexer connected in series with said processor elements for directing data around said processor elements in the event any of said scan registers generates said different scan output signal.
Claim 7
Dependent Claim
27 words
The fault detection circuit recited in claim 1 further comprising means for altering said test bits for fully testing the logic performance of all said processor elements.
Claim 8
Dependent Claim
135 words
A fault detection circuit for use on a unitary integrated circuit chip with a plurality of identical processor elements configured in a serial arrangement and forming a systolic array; the fault detection circuit comprising: a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element; a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.
Claim 9
Dependent Claim
135 words
A fault detection circuit for use on a unitary integrated circuit chip with a plurality of identical processor elements configured in a serial arrangement and forming a systolic array; the fault detection circuit comprising: a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element; a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.
Claim 10
Dependent Claim
99 words
The fault detection circuit recited in claim 7 further comprising: a plurality of two parallel-input multiplexers, one such multiplexer being connected between each adjacent pair of said processor elements, one of said multiplexer parallel inputs being connected to the immediately adjacent processor element and the other of said multiplexer parallel inputs being connected to the processor element immediately preceding said immediately adjacent processor element; and means for switching each said multiplexer between said respective parallel inputs depending upon whether the scan output signal of said immediately adjacent processor element is different or identical to the remaining scan output signals.
Claim 11
Dependent Claim
65 words
The fault detection circuit recited in claim B wherein said switching means comprises a switching signal terminal on each said multiplexer and a register for storing a plurality of switching signals, said switching signals being applied to respective ones of said switching signal terminals, the state of each such switching signal being controlled in accordance with the plurality of encoded signals generated by said encoder.
Claim 12
Dependent Claim
48 words
The fault detection circuit recited in claim 9 wherein said switching signals are also applied to said comparator and wherein said comparator comprises means for inhibiting said error signal after the multiplexer corresponding to a scan register which has generated a different scan output signal, has been switched.
Claim 13
Dependent Claim
44 words
The fault detection circuit recited in claim 7 further comprising: at least one, two parallel-input multiplexer connected in series with said processor elements for directing data around said processor elements in the event any of said scan registers generates said different scan output signal.
Claim 14
Dependent Claim
27 words
The fault detection circuit recited in claim 7 further comprising means for altering said test bits for fully testing the logic performance of all said processor elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |