Dynamic semiconductor memory device comprising a switching transistor and storage capacitor

Claim 2

A memory cell of a dynamic semiconductor memory device, said memory cell comprising: a silicon substrate having a trench formed in a surface thereof; a first insulating film formed at a first thickness to cover an interior of said trench, said first insulating film terminating at one edge of said trench, said one edge of said trench being defined by said surface of said silicon substrate at an opening of said trench; a capacitor comprising (a) a lower electrode having an outer surface formed on said first insulating film and having one end terminating at said edge of said trench, (b) a second insulating film formed at a second thickness on said lower electrode, and (c) an upper electrode formed on said second insulating film; and a switching transistor comprising (a) a channel region formed at the surface of the silicon substrate having first and second ends, said first end of said channel region adjoining said one end of said lower electrode of said capacitor at said one edge of said trench, (b) a drain region adjoining said second end of said channel region, and (c) a gate electrode formed over said channel region and separated from said channel region by a gate insulating film; said first thickness of said first insulating film being sufficient to isolate said lower electrode from said silicon substrate; said switching transistor having at least a portion of a source region formed of said lower electrode of said capacitor.

Claim 3

A memory cell as recited in claim 1, wherein: said lower electrode is formed of at least a portion of a poly-silicon film deposited on said first insulating layer; said switching transistor is an MOS type transistor; said channel region is formed in a silicon epitaxial layer epitaxially grown on said surface of said silicon substrate simultaneously with a deposition of said poly-silicon film; said first thickness of said first insulating film being such that said first insulating film prevents the memory cell from interfering with other parts of the dynamic semiconductor memory device resulting from leakage current in the memory cell due to punch through.

Claim 4

A memory cell as recited in claim 1, wherein said first thickness film is about 1500 angstroms, and said second thickness is about 200 angstroms.

Claim 5

A memory cell as recited in claim 2, wherein said first thickness film is about 1500 angstroms, and said second thickness is about 200 angstroms.

Claim 6

A memory cell of a dynamic semiconductor memory device, said memory cell comprising: a silicon substrate having a trench formed in a surface thereof; a first insulating film formed at a first thickness to cover an interior of said trench, said first insulating film terminating at one edge of said trench, said one edge of said trench being defined by said surface of said silicon substrate at an opening of said trench; a capacitor comprising (a) a lower electrode having an outer surface formed on said first insulating film and having one end terminating at said edge of said trench, (b) a second insulating film formed at a second thickness on said lower electrode, and (c) an upper electrode formed on said second insulating film; and a switching transistor comprising (a) a channel region formed at the surface of the silicon substrate having first and second ends, said first end of said channel region adjoining said one end of said lower electrode of said capacitor at said one edge of said trench, (b) a drain region adjoining said second end of said channel region, and (c) a gate electrode formed over said channel region and separated from said channel region by a gate insulating film; said first thickness of said first insulating film being sufficient to isolate said lower electrode from said silicon substrate; said switching transistor having at least a portion of a source region formed of said lower electrode of said capacitor; wherein said gate electrode of said switching transistor partially extends over said upper electrode of said capacitor.

Claim 7

A memory cell of a dynamic semiconductor memory device, said memory cell comprising: a silicon substrate having a trench formed in a surface thereof; a first insulating film formed at a first thickness to cover an interior of said trench, said first insulating film terminating at one edge of said trench, said one edge of said trench being defined by said surface of said silicon substrate at an opening of said trench; a capacitor comprising (a) a lower electrode having an outer surface formed on said first insulating film and having one end terminating at said edge of said trench, (b) a second insulating film formed at a second thickness on said lower electrode, and (c) an upper electrode formed on said second insulating film; and a switching transistor comprising (a) a channel region formed at the surface of the silicon substrate having first and second ends, said first end of said channel region adjoining said one end of said lower electrode of said capacitor at said one edge of said trench, (b) a drain region adjoining said second end of said channel region, and (c) a gate electrode formed over said channel region and separated from said channel region by a gate insulating film; said first thickness of said first insulating film being sufficient to isolate said lower electrode from said silicon substrate; said switching transistor having at least a portion of a source region formed of said lower electrode of said capacitor; wherein said gate electrode of said switching transistor partially extends over said upper electrode of said capacitor.

Claim 8

A memory cell as recited in claim 5, wherein: said lower electrode is formed of at least a portion of a poly-silicon film deposited on said first insulating layer; said switching transistor is an MOS type transistor; said channel region is formed in a silicon epitaxial layer epitaxially grown on said surface of said silicon substrate simultaneously with a deposition of said poly-silicon film; said first thickness of said first insulating film being such that said first insulating film prevents the memory cell from interfering with other parts of the dynamic semiconductor memory device resulting from leakage current in the memory cell due to punch through.

Claim 9

A memory cell of a dynamic semiconductor memory device, said memory cell comprising: a silicon substrate having a trench formed in a surface thereof; a first insulating film formed at a first thickness to cover an interior of said trench, said first insulating film terminating at one edge of said trench, said one edge of said trench being defined by said surface of said silicon substrate at an opening of said trench; a capacitor comprising (a) a lower electrode having an outer surface formed on said first insulating film and having one end terminating at said edge of said trench, (b) a second insulating film formed at a second thickness on said lower electrode, and (c) an upper electrode formed on said second insulating film; and a switching transistor comprising (a) a channel region formed at the surface of the silicon substrate having first and second ends, said first end of said channel region adjoining said one end of said lower electrode of said capacitor at said one edge of said trench, (b) a drain region adjoining said second end of said channel region, and (c) a gate electrode formed over said channel region and separated from said channel region by a gate insulating film; said first thickness of said first insulating film being sufficient to isolate said lower electrode from said silicon substrate; said switching transistor having at least a portion of a source region formed of said lower electrode of said capacitor; wherein said channel region and said drain region and said one end of said lower electrode extend in a same plane along said surface of said substrate.

Claim 10

A memory cell of a dynamic semiconductor memory device, said memory cell comprising: a silicon substrate having a trench formed in a surface thereof; a first insulating film formed at a first thickness to cover an interior of said trench, said first insulating film terminating at one edge of said trench, said one edge of said trench being defined by said surface of said silicon substrate at an opening of said trench; a capacitor comprising (a) a lower electrode having an outer surface formed on said first insulating film and having one end terminating at said edge of said trench, (b) a second insulating film formed at a second thickness on said lower electrode, and (c) an upper electrode formed on said second insulating film; and a switching transistor comprising (a) a channel region formed at the surface of the silicon substrate having first and second ends, said first end of said channel region adjoining said one end of said lower electrode of said capacitor at said one edge of said trench, (b) a drain region adjoining said second end of said channel region, and (c) a gate electrode formed over said channel region and separated from said channel region by a gate insulating film; said first thickness of said first insulating film being sufficient to isolate said lower electrode from said silicon substrate; said switching transistor having at least a portion of a source region formed of said lower electrode of said capacitor; wherein said channel region and said drain region and said one end of said lower electrode extend in a same plane along said surface of said substrate.

Claim 11

A memory cell as recited in claim 6, wherein: said lower electrode is formed of at least a portion of a poly-silicon film deposited on said first insulating layer; said switching transistor is an MOS type transistor; said channel region is formed in a silicon epitaxial layer epitaxially grown on said surface of said silicon substrate simultaneously with a deposition of said poly-silicon film; said first thickness of said first insulating film being such that said first insulating film prevents the memory cell from interfering with other parts of the dynamic semiconductor memory device resulting from leakage current in the memory cell due to punch through.