Variable frequency clock pulse generator for microcomputer

Claim 1

A one-chip microprocessor having a clock pulse generator on the same chip comprising: means for receiving clock pulses; dividing means connected to said receiving means, for successively dividing said clock pulses a plurality of times and for producing a corresponding plurality of clock pulse signals having a slowest and a plurality of faster clock pulse signals, each of said plurality of clock pulse signals having leading and trailing edges and having different pulse widths, wherein one period of the slowest of said plurality of clock pulse signals is equal to a respective predetermined integer number of periods of each of the faster clock pulse signals, said one period and said periods of each of the faster clock pulse signals each defining a cycle, wherein for any pair of said clock pulse signals, a predetermined one of the leading and trailing edges of one of the pair of clock pulse signals having a longer period coincides with a predetermined one of the leading and trailing edges of the other clock pulse signal of the pair having a shorter period; a plurality of gate circuits connected to said dividing means for selectively supplying only one of said clock pulse signals produced by said dividing means, at a time; an output terminal arrangement connected to said plurality of gate circuits for outputting said one clock pulse signal to said microprocessor; a first pair and second pair of input terminals connected to said plurality of gate circuits for selectively controlling said plurality of gate circuits in response to control signals supplied to said first pair or second pair of input terminals; and a third input terminal and control means connected to said first pair and second pair of input terminals for determining which of said first and second pairs of input terminals control said plurality of gate circuits.