Insulated gate field-effect transistor with pulse-shaped doping

Claim 1

An integrated circuit formed on at least a portion of a silicon substrate having a principal surface, the integrated circuit comprising a MOSFET comprising: a gate oxide layer of thickness t ox overlying a portion of the substrate; a source region, and a drain region spaced from the source region, each defined in a portion of the substrate and extending to a junction depth t j beneath the principal surface and each having a first predominant carrier type; and first and second channel regions defined within the substrate and located between the source and drain regions, the first channel region at least partially overlying the second channel region, and the gate oxide layer overlying the first channel region, and the first and second channel regions being doped such that each has a second predominant carrier type opposite to the first carrier type, and the second channel region has a higher carrier density than the first channel region, characterized in that a) the first channel region extends from the principal surface to a depth, to be referred to as t Si , which is less than or equal to about 500 Å, b) the second channel region extends substantially from t Si to a depth that is is less than or equal to about t j , c) the room-temperature carrier density in the first channel region is less than about 2×10 17 cm -3 ; and d) the room-temperature carrier density in the second channel region is greater than about 5×10 17 cm -3 .