Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
392 words
A short channel insulated gate field effect transistor having a deep ion implantation layer, said transistor comprising: (a) a substrate of semiconductor material of a first conductivity type, having a major surface; (b) a source region of a second conductivity type opposite in polarity to the first conductivity type, the source region being formed in and extending under the major surface; (c) a drain region of the second conductivity type, formed in and extending under the major surface, the drain region being separated from the source region by the substrate material; (d) a channel region in the substrate situated between the source and drain regions, the channel region comprising a gate depletion region and a channel layer, wherein current flows through the channel layer; (e) a gate electrode positioned above the channel region and extending on a gate insulator film formed on the major surface of at least the channel region; (f) a source depletion layer and said gate depletion layer being formed in the substrate by the electric fields of the source region and the gate electrode; (g) a source depletion boundary defined between the substrate and the source depletion layer in the absence of a back gate voltage on the substrate; (h) a gate depletion boundary defined between the substrate and maximum depletion layer formed in the substrate in the absence of the back gate voltage; and (i) a deep ion implanted layer of the first conductivity type formed in a deep portion of the channel region, wherein the gate depletion boundary is located in the deep ion implanted layer and the density of the deep ion implanted layer is such that a recessed portion is defined in the source depletion boundary, the recessed portion extending towards the source region; (j) wherein the angle θ formed between the surface of the substrate and an imaginary line extending from the junction of the source region and the channel region on the surface of the substrate to the intersection of the gate depletion boundary and the source depletion boundary is greater than 90° whereby the intersection of the gate depletion boundary and the source depletion boundary is displaced towards the source side of an imaginary line perpendicular to the major surface, the imaginary line passing through the junction of the source region and the channel region on the surface of the substrate.
Claim 2
Dependent Claim
392 words
A short channel insulated gate field effect transistor having a deep ion implantation layer, said transistor comprising: (a) a substrate of semiconductor material of a first conductivity type, having a major surface; (b) a source region of a second conductivity type opposite in polarity to the first conductivity type, the source region being formed in and extending under the major surface; (c) a drain region of the second conductivity type, formed in and extending under the major surface, the drain region being separated from the source region by the substrate material; (d) a channel region in the substrate situated between the source and drain regions, the channel region comprising a gate depletion region and a channel layer, wherein current flows through the channel layer; (e) a gate electrode positioned above the channel region and extending on a gate insulator film formed on the major surface of at least the channel region; (f) a source depletion layer and said gate depletion layer being formed in the substrate by the electric fields of the source region and the gate electrode; (g) a source depletion boundary defined between the substrate and the source depletion layer in the absence of a back gate voltage on the substrate; (h) a gate depletion boundary defined between the substrate and maximum depletion layer formed in the substrate in the absence of the back gate voltage; and (i) a deep ion implanted layer of the first conductivity type formed in a deep portion of the channel region, wherein the gate depletion boundary is located in the deep ion implanted layer and the density of the deep ion implanted layer is such that a recessed portion is defined in the source depletion boundary, the recessed portion extending towards the source region; (j) wherein the angle θ formed between the surface of the substrate and an imaginary line extending from the junction of the source region and the channel region on the surface of the substrate to the intersection of the gate depletion boundary and the source depletion boundary is greater than 90° whereby the intersection of the gate depletion boundary and the source depletion boundary is displaced towards the source side of an imaginary line perpendicular to the major surface, the imaginary line passing through the junction of the source region and the channel region on the surface of the substrate.
Claim 3
Dependent Claim
35 words
The insulated gate field effect transistor according to claim 1, wherein a middle portion of said deep ion implantation layer is formed at a level shallower than the lowest point of the gate depletion boundary.
Claim 4
Dependent Claim
31 words
The insulated gate field effect transistor according to claim 1, wherein said deep ion implantation layer in the channel region has a depth deeper than the depth of the source region.
Claim 5
Dependent Claim
30 words
The insulated gate effect transistor according to claim 1, wherein said deep ion implantation layer in the channel region has a depth shallower than the depth of the source region.