Arrangement for high speed testing of field-effect transistors and memory cells employing the same

Claim 3

A method as defined in claim 1 wherein said reference potential is one-half said potential difference.

Claim 4

A method as defined in claim 1 wherein said field-effect transistor to be tested is a P-channel field-effect transistor, wherein said weak field-effect transistor is an N-channel field-effect transistor, and wherein said N-channel field-effect transistor is configured to source one-tenth or less current than said P-channel field-effect transistor can source.

Claim 5

A method as defined in claim 1 wherein said field-effect transistor to be tested is an N-channel field-effect transistor, wherein said weak field-effect transistor is a P-channel field-effect transistor, and wherein said P-channel field-effect transistor is configured to source one-fifth or less current than said N-channel field-effect transistor can source.

Claim 6

An arrangement for testing the operability of a field-effect transistor to be tested comprising: a second field-effect transistor coupled in series relation to said field-effect transistor to be tested to form a series combination of said field-effect transistors, said second field-effect transistor being opposite in type with respect to said field-effect transistor to be tested and having a lower current sourcing capability than said field-effect transistor to be tested; a first voltage source coupled to one of said field-effect transistors; a second voltage source coupled to the other one of said field-effect transistors, said first and second voltage sources providing a potential difference across said series combination of said field-effect transistors; means for applying coincident turn-on potentials to said field-effect transistors; and sensing means having a sensing input coupled between said field-effect transistor to be tested and said second field-effect transistor for sensing the potential at said sensing input when said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 7

An arrangement for testing the operability of a field-effect transistor to be tested comprising: a second field-effect transistor coupled in series relation to said field-effect transistor to be tested to form a series combination of said field-effect transistors, said second field-effect transistor being opposite in type with respect to said field-effect transistor to be tested and having a lower current sourcing capability than said field-effect transistor to be tested; a first voltage source coupled to one of said field-effect transistors; a second voltage source coupled to the other one of said field-effect transistors, said first and second voltage sources providing a potential difference across said series combination of said field-effect transistors; means for applying coincident turn-on potentials to said field-effect transistors; and sensing means having a sensing input coupled between said field-effect transistor to be tested and said second field-effect transistor for sensing the potential at said sensing input when said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 8

An arrangement as defined in claim 5 wherein said field-effect transistor to be tested is a P-channel field-effect transistor having a source, a drain, and a gate, wherein said second field-effect transistor is an N-channel field-effect transistor having a source, a drain, and a gate, wherein said drain of said P-channel field-effect transistor is coupled to said drain of said N-channel field-effect transistor, wherein said first voltage source is coupled to said source of said P-channel field-effect transistor, wherein said second voltage source is coupled to said source of said N-channel field-effect transistor, and wherein said first voltage source is more positive than said second voltage source.

Claim 9

An arrangement as defined in claim 6 wherein said sensing means comprises a sense amplifier including a reference input and wherein said arrangement further includes a reference voltage source for applying a reference voltage potential to said reference input.

Claim 10

An arrangement as defined in claim 7 wherein said reference voltage source provides a reference voltage of one-half said potential difference across said series combination of field-effect transistors.

Claim 11

An arrangement as defined in claim 8 wherein said P-channel field-effect transistor is configured to source at least ten times more current than said N-channel field-effect transistor.

Claim 12

An arrangement as defined in claim 8 further including charging means for precharging said sensing input to said reference voltage potential before said field-effect transistors are turned on.

Claim 13

An arrangement as defined in claim 5 wherein said field-effect transistor to be tested is an N-channel field-effect transistor having a source, a drain, and a gate, wherein said second field-effect transistor is a P-channel field-effect transistor having a source, a drain, and a gate, wherein said drain of said N-channel field-effect transistor is coupled to said drain of said P-channel field-effect transistor, wherein said first voltage source is coupled to said source of said P-channel field-effect transistor, wherein said second voltage source is coupled to said source of said N-channel field-effect transistor, and wherein said first voltage source is more positive than said second voltage source.

Claim 14

An arrangement as defined in claim 11 wherein said sensing means comprises a sense amplifier including a reference input and wherein said arrangement further includes a reference voltage source for applying a reference voltage potential to said reference input.

Claim 15

An arrangement as defined in claim 12 wherein said reference voltage source provides a reference voltage of one-half said potential difference across said series combination of field-effect transistors.

Claim 16

An arrangement as defined in claim 13 wherein said N-channel field-effect transistor is configured to source at least five times more current than said P-channel field-effect transistor.

Claim 17

An arrangement as defined in claim 13 further including charging means for precharging said sensing input to said reference voltage potential before said field-effect transistors are turned on.

Claim 18

An arrangement for testing the operability of a field-effect transistor to be tested of a memory cell within a memory cell array, said memory cell being associated with a row conductor and at least one column conductor, said field-effect transistor to be tested being coupled between a first source of fixed potential and said column conductor, said arrangement comprising: a second source of fixed potential; a second field-effect transistor coupled between said column conductor and said second source of fixed potential to form a series combination of said field-effect transistor to be tested and said second field-effect transistor between said first and second sources of fixed potential, said second field-effect transistor being of opposite type with respect said field-effect transistor to be tested and having a lower current sourcing capability than said field-effect transistor to be tested; means for applying coincident turn-on potentials to said field-effect transistor to be tested and said second field-effect transistor; and sensing means having a sensing input coupled to said column conductor between said field-effect transistor to be tested and said second field-effect transistor for sensing the potential at said sensing input when said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 19

An arrangement for testing the operability of a field-effect transistor to be tested of a memory cell within a memory cell array, said memory cell being associated with a row conductor and at least one column conductor, said field-effect transistor to be tested being coupled between a first source of fixed potential and said column conductor, said arrangement comprising: a second source of fixed potential; a second field-effect transistor coupled between said column conductor and said second source of fixed potential to form a series combination of said field-effect transistor to be tested and said second field-effect transistor between said first and second sources of fixed potential, said second field-effect transistor being of opposite type with respect said field-effect transistor to be tested and having a lower current sourcing capability than said field-effect transistor to be tested; means for applying coincident turn-on potentials to said field-effect transistor to be tested and said second field-effect transistor; and sensing means having a sensing input coupled to said column conductor between said field-effect transistor to be tested and said second field-effect transistor for sensing the potential at said sensing input when said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 20

An arrangement as defined in claim 16 wherein said field-effect transistor to be tested is a P-channel field-effect transistor having a source, a drain, and a gate, wherein said second field-effect transistor is an N-channel field-effect transistor having a source, a drain, and a gate, wherein said drain of said P-channel field-effect transistor is coupled to said drain of said N-channel field-effect transistor, wherein said first voltage source is coupled to said source of said P-channel field-effect transistor, wherein said second voltage source is coupled to said source of said N-channel field-effect transistor, and wherein said first voltage source is more positive than said second voltage source.

Claim 21

An arrangement as defined in claim 17 wherein said sensing means comprises a sense amplifier including a reference input and wherein said arrangement further includes a reference voltage source for applying a reference voltage potential to said reference input.

Claim 22

An arrangement as defined in claim 18 wherein said reference voltage source provides a reference voltage of one-half the potential difference between said first and second sources of fixed potential.

Claim 23

An arrangement as defined in claim 19 wherein said P-channel field-effect transistor is configured to source at least ten times more current than said N-channel field-effect transistor.

Claim 24

An arrangement as defined in claim 19 further including charging means for precharging said sensing input to said reference voltage potential before said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 25

An arrangement as defined in claim 16 wherein said field-effect transistor to be tested is an N-channel field-effect transistor having a source, a drain, and a gate, wherein said second field-effect transistor is a P-channel field-effect transistor having a source, a drain, and a gate, wherein said drain of said N-channel field-effect transistor is coupled to said drain of said P-channel field-effect transistor, wherein said first voltage source is coupled to said source of said P-channel field-effect transistor, wherein said second voltage source is coupled to said source of said N-channel field-effect transistor, and wherein said first voltage source is more positive than said second voltage source.

Claim 26

An arrangement as defined in claim 22 wherein said sensing means comprises a sense amplifier including a reference input and wherein said arrangement further includes a reference voltage source for applying a reference voltage potential to said reference input.

Claim 27

An arrangement as defined in claim 23 wherein said reference voltage source provides a reference voltage of one-half the potential difference between said first and second sources of fixed potential.

Claim 28

An arrangement as defined in claim 24 wherein said N-channel field-effect transistor is configured to source at least five times more current than said P-channel field-effect transistor.

Claim 29

An arrangement as defined in claim 24 further including charging means for precharging said sensing input to said reference voltage potential before said turn-on potentials are coincidently applied to said field-effect transistors.

Claim 30

In a memory array of the type including a plurality of memory cells arranged in rows and columns, each said memory cell being associated with a unique combination of a row conductor and a pair of first and second column conductor, each said memory cell including a cross coupled latch having first and second sides with each said side including series coupled P and N-channel field-effect transistors, and a pass transistor having a control gate coupled to the associated row conductors and being coupled between a respective one of said column conductors and the common junction of the series coupled P and N-channel field-effect transistors, an arrangement for testing the operability of said P and N-channel field-effect transistors and comprising: sensing means associated with each said column of memory cells, said sensing means including a first input coupled to said first column conductor of said pair of column conductors and a second input coupled to said second column conductor of said pair of column conductors for sensing the potential difference between said first and second column conductors; a first weak P-channel field-effect transistor coupled to said sensing means first input; a first weak N-channel field-effect transistor coupled to said sensing means first input; a second weak P-channel field-effect transistor coupled to said sensing means second input; a second weak N-channel field-effect transistor coupled to said sensing means second input; said weak P-channel field-effect transistors having a lower current sourcing capability than said memory cell N-channel field-effect transistors and said weak N-channel field-effect transistors having a lower current sourcing capability than said memory cell P-channel field-effect transistors; a first transfer gate coupling said sensing means first input to said first column conductor; and a second transfer gate coupling said sensing means second input to said second column conductor.

Claim 31

In a memory array of the type including a plurality of memory cells arranged in rows and columns, each said memory cell being associated with a unique combination of a row conductor and a pair of first and second column conductor, each said memory cell including a cross coupled latch having first and second sides with each said side including series coupled P and N-channel field-effect transistors, and a pass transistor having a control gate coupled to the associated row conductors and being coupled between a respective one of said column conductors and the common junction of the series coupled P and N-channel field-effect transistors, an arrangement for testing the operability of said P and N-channel field-effect transistors and comprising: sensing means associated with each said column of memory cells, said sensing means including a first input coupled to said first column conductor of said pair of column conductors and a second input coupled to said second column conductor of said pair of column conductors for sensing the potential difference between said first and second column conductors; a first weak P-channel field-effect transistor coupled to said sensing means first input; a first weak N-channel field-effect transistor coupled to said sensing means first input; a second weak P-channel field-effect transistor coupled to said sensing means second input; a second weak N-channel field-effect transistor coupled to said sensing means second input; said weak P-channel field-effect transistors having a lower current sourcing capability than said memory cell N-channel field-effect transistors and said weak N-channel field-effect transistors having a lower current sourcing capability than said memory cell P-channel field-effect transistors; a first transfer gate coupling said sensing means first input to said first column conductor; and a second transfer gate coupling said sensing means second input to said second column conductor.

Claim 32

An arrangement as defined in claim 27 wherein said memory cell P-channel field-effect transistors are configured to source at least ten times more current than said weak N-channel field-effect transistors.

Claim 33

An arrangement as defined in claim 27 wherein said memory cell N-channel field-effect transistors are configured to source at least five times more current than said weak P-channel field-effect transistors.

Claim 34

An arrangement as defined in claim 27 wherein said sensing means comprises a sense amplifier.