Cmos ecl/ttl output circuit

Claim 2

An output circuit comprising: first and second power sources; an input terminal receiving an input voltage; an output terminal; a first MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; a second MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; a first differential amplifier for comparing a first reference voltage with a voltage at said output terminal; a second differential amplifier for comparing a second reference voltage lower than said first reference voltage with said voltage at said output terminal; a first logic gate for receiving an output from said first differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said first MOS transistor; and a second logic gate for receiving an output from said second differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said second MOS transistor.

Claim 3

The circuit according to claim 1, wherein said first reference voltage and said voltage at said output terminal are applied to a non-inverting input terminal of said first differential amplifier and to an inverting input terminal of said first differential amplifier; said second reference voltage and said voltage at said output terminal are applied to a non-inverting input terminal of said second differential amplifier and to an inverting input terminal of said second differential amplifier; said first logic gate is a two-input NAND gate; said second logic gate is a two-input NOR gate; said first MOS transistor is a p-channel MOS transistor; and said second MOS transistor is an n-channel MOS transistor.

Claim 4

The circuit according to claim 1, wherein said first differential amplifier consists of a first pair of MOS transistors having gates for receiving said first reference voltage and said voltage at said output terminal and a first current supplying circuit for equalizing values of currents flowing through current paths of said MOS transistors constituting said first pair of MOS transistors; and said second differential amplifier consists of a second pair of MOS transistors having gates for receiving said second reference voltage and said voltage at said output terminal and a second current supplying circuit for equalizing values of currents flowing through current paths of said MOS transistors constituting said second pair of MOS transistors.

Claim 5

The circuit according to claim 3, wherein said first current supplying circuit is a current mirror circuit consisting of a pair of MOS transistors of a conductivity type different from a conductivity type of said first pair of MOS transistors; and said second current supplying circuit is a current mirror circuit consisting of a pair of MOS transistors of a conductivity type different from a conductivity type of said second pair of MOS transistors.

Claim 6

The circuit according to claim 3, further comprising: a first through current protection MOS transistor coupled between one current terminal of said first pair of MOS transistors of the first differential amplifier and said second power source; a second through current protection MOS transistor coupled between one current terminal of said second pair of MOS transistors of said second differential amplifier and said second power source; and wherein said input voltage and an input obtained by inverting said input voltage are complimentarily input to gates of said first and second through current protection MOS transistors.

Claim 7

The circuit according to claim 1, further comprising: a first buffer circuit coupled between said first logic gate and said control gate of said first MOS transistor, and a second buffer circuit coupled between said second logic gate and said control gate of said second MOS transistor.

Claim 8

The circuit according to claim 6, wherein each of said first and second buffer circuits consists of two inverters connected in series with each other.

Claim 9

The output circuit according to claim 1, wherein said input voltage is a CMOS level signal and said output signal is a TTL level signal.

Claim 10

The output circuit according to claim 8, wherein said first reference voltage is a TTL high level signal and said second reference voltage is a TTL low level voltage signal.

Claim 11

The output circuit according to claim 1, wherein said input voltage is a CMOS level signal and said output signal is a ECL level signal.

Claim 12

The output circuit according to claim 10, wherein said first reference voltage is an ECL high level signal and said second reference voltage is an ECL low level voltage signal.

Claim 13

An output circuit, comprising: first and second power sources; an input terminal receiving an input voltage; an output terminal; a p-channel MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; an n-channel MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; a first differential amplifier having a noninverting input terminal and an inverting input terminal which receive a first reference voltage and a voltage at said output terminal, respectively; a second differential amplifier having a noninverting input terminal and an inverting input terminal which receive a second reference voltage lower than said first reference voltage and the voltage at said output terminal, respectively; a two-input NAND gate for receiving an output from said first differential amplifier and said input voltage, said two-input NAND gate having an output terminal connected to said control gate of said first MOS transistor; and a two-input NOR gate for receiving an output from said second differential amplifier and said input voltage, said two-input NOR gate having an output terminal connected to said control gate of said second MOS transistor.

Claim 14

An output circuit, comprising: first and second power sources; an input terminal receiving an input voltage; an output terminal; a p-channel MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; an n-channel MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; a first differential amplifier having a noninverting input terminal and an inverting input terminal which receive a first reference voltage and a voltage at said output terminal, respectively; a second differential amplifier having a noninverting input terminal and an inverting input terminal which receive a second reference voltage lower than said first reference voltage and the voltage at said output terminal, respectively; a two-input NAND gate for receiving an output from said first differential amplifier and said input voltage, said two-input NAND gate having an output terminal connected to said control gate of said first MOS transistor; and a two-input NOR gate for receiving an output from said second differential amplifier and said input voltage, said two-input NOR gate having an output terminal connected to said control gate of said second MOS transistor.

Claim 15

The circuit according to claim 12, wherein said first differential amplifier consists of a first pair of MOS transistors having gates for receiving said first reference voltage and said voltage at said output terminal and a first current supplying circuit for equalizing values of currents flowing through current paths of said MOS transistors constituting said first pair of MOS transistors; and said second differential amplifier consists of a second pair of MOS transistors having gates for receiving said second reference voltage and said voltage at said output terminal and a second current supplying circuit for equalizing values of currents flowing through current paths of said MOS transistors constituting said second pair of MOS transistors.

Claim 16

The circuit according to claim 13, wherein said first current supplying circuit is a current mirror circuit consisting of a pair of MOS transistors of a conductivity type different from a conductivity type of said first pair of MOS transistors; and said second current supplying circuit is a current mirror circuit consisting of a pair of MOS transistors of a conductivity type different from a conductivity type of said second pair of MOS transistors.

Claim 17

The circuit according to claim 13, further comprising: a first through current protection MOS transistor coupled between one current terminal of said first pair of MOS transistors of the first differential amplifier and said second power source; a second through current protection MOS transistor coupled between one current terminal of said second pair of MOS transistors of said second differential amplifier and said second power source; and wherein said input voltage and an input obtained by inverting said input voltage are complimentarily input to gates of said first and second through current protection MOS transistors respectively.

Claim 18

An output circuit for receiving an input logic level signal of a first logic type and outputting an output logic signal of a second logic type, said output circuit, comprising: an input terminal receiving said input logic level signal; an output terminal outputting said output logic level signal; a MOS transistor having a control gate and first and second current terminals respectively connected between said ground source and said output terminal; a differential amplifier for comparing a reference voltage of the second logic type with a voltage at said output terminal; and a logic gate having a first input terminal for receiving an output from said differential amplifier, a second input terminal for receiving said input logic level signal, and an output terminal coupled to said control gate of said MOS transistor.

Claim 19

An output circuit for receiving an input logic level signal of a first logic type and outputting an output logic signal of a second logic type, said output circuit, comprising: an input terminal receiving said input logic level signal; an output terminal outputting said output logic level signal; a MOS transistor having a control gate and first and second current terminals respectively connected between said ground source and said output terminal; a differential amplifier for comparing a reference voltage of the second logic type with a voltage at said output terminal; and a logic gate having a first input terminal for receiving an output from said differential amplifier, a second input terminal for receiving said input logic level signal, and an output terminal coupled to said control gate of said MOS transistor.

Claim 20

The circuit according to claim 16, wherein said logic gate is a NAND gate.

Claim 21

The output circuit according to claim 16, wherein said input logic level signal is a CMOS logic level signal and said output logic level signal is an ECL logic level signal.

Claim 22

An output circuit, comprising: first and second power sources; an input terminal receiving an input voltage; an output terminal; a first MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; a second MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; a differential amplifier for comparing a reference voltage with a voltage at said output terminal; a first logic gate for receiving an output from said differential amplifier and said input voltage, said first logic gate having an output terminal connected to said control gate of said first MOS transistor; and a second logic gate for inverting said input voltage and having an output terminal connected to said control gate of said second MOS transistor.

Claim 23

An output circuit, comprising: first and second power sources; an input terminal receiving an input voltage; an output terminal; a first MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; a second MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; a differential amplifier for comparing a reference voltage with a voltage at said output terminal; a first logic gate for receiving an output from said differential amplifier and said input voltage, said first logic gate having an output terminal connected to said control gate of said first MOS transistor; and a second logic gate for inverting said input voltage and having an output terminal connected to said control gate of said second MOS transistor.

Claim 24

The circuit according to claim 19, wherein said second logic gate is an inverter.

Claim 25

The circuit according to claim 20, wherein said differential amplifier consists of a pair of MOS transistors for respectively receiving said reference voltage and the voltage at said output terminal, a current supplying circuit for equalizing currents flowing through current paths of said MOS transistors constituting said pair MOS transistors, and a through current protection MOS transistors having a gate receiving said input voltage and which is coupled between one current terminal of said path of MOS transistors and said second power source voltage.

Claim 26

An output circuit for receiving an output logic level signal of a first logic type and outputting an output logic level signal of a second logic type, said output circuit comprising: first and second power sources; an input terminal receiving said input logic level signal; an output terminal for outputting said output logic level signal; a first MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; a second MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; check a first differential amplifier for comparing a first reference voltage with a voltage at said output terminal; a second differential amplifier for comparing a second reference voltage lower than said first reference voltage with said voltage at said output terminal; a first logic gate for receiving an output from said first differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said first MOS transistor; and a second logic gate for receiving an output from said second differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said second MOS transistor.

Claim 27

An output circuit for receiving an output logic level signal of a first logic type and outputting an output logic level signal of a second logic type, said output circuit comprising: first and second power sources; an input terminal receiving said input logic level signal; an output terminal for outputting said output logic level signal; a first MOS transistor having a control gate and first and second current terminals respectively coupled between said first power source and said output terminal; a second MOS transistor having a control gate and first and second current terminals respectively coupled between said second power source and said output terminal; check a first differential amplifier for comparing a first reference voltage with a voltage at said output terminal; a second differential amplifier for comparing a second reference voltage lower than said first reference voltage with said voltage at said output terminal; a first logic gate for receiving an output from said first differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said first MOS transistor; and a second logic gate for receiving an output from said second differential amplifier and said input voltage, said first logic gate having an output terminal connected to said gate of said second MOS transistor.

Claim 28

The output circuit according to claim 22, wherein said input signal is a CMOS level signal and said output signal is a TTL level signal.

Claim 29

The output circuit according to claim 22, wherein said first reference voltage is a TTL high level signal and said second reference voltage is a TTL low level voltage signal.

Claim 30

The output circuit according to claim 22, wherein said input signal is a CMOS level signal and said output signal is a ECL level signal.

Claim 31

The output circuit according to claim 25, wherein said first reference voltage is an ECL high level signal and said second reference voltage is an ECL low level voltage signal.

Claim 32

An output circuit, comprising: an input terminal receiving an input voltage; an output terminal; a ground potential source; a MOS transistor having a control gate and first and second current terminals respectively connected between said ground potential source and said output terminal; a differential amplifier for comparing a reference voltage with a voltage at said output terminal; and a NAND gate having a first input terminal receiving an output of said differential amplifier, a second input terminal receiving the input voltage, and an output terminal coupled to said control gate of said MOS transistor.

Claim 33

An output circuit, comprising: an input terminal receiving an input voltage; an output terminal; a ground potential source; a MOS transistor having a control gate and first and second current terminals respectively connected between said ground potential source and said output terminal; a differential amplifier for comparing a reference voltage with a voltage at said output terminal; and a NAND gate having a first input terminal receiving an output of said differential amplifier, a second input terminal receiving the input voltage, and an output terminal coupled to said control gate of said MOS transistor.