Semiconductor integrated circuit having a dummy lead and shaped inner leads

Claim 2

A semiconductor integrated circuit comprising: a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposing end portions and a predetermined internal volume; a plurality of leads, each said lead including an outer lead portion external to said cavity, a first inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width narrower than said first width extending to said semiconductor chip, one of said plurality of leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage branching into a plurality of adjacent branched second inner lead portions; a plurality of metal wires, each said metal wire electrically connecting one of said second inner lead portion and one said pad electrode; and a dummy lead disposed between said lead supplying the power voltage and another lead, said dummy lead including an outer lead portion external to said cavity, and an inner dummy lead portion having a width equal to the first radial width, and a termination at one said end portion of said cavity adjacent said housing, wherein the termination of said inner dummy lead portion provides sufficient area within said housing for said plurality of branched second inner lead portions of said lead supplying the power voltage.

Claim 3

The semiconductor integrated circuit according to claim 1, wherein said second inner lead portion of said lead supplying power voltage branches into a plurality of branched second lead portions in one said end portion of said housing.

Claim 4

The semiconductor integrated circuit according to claim 2, wherein said second inner lead portion of said lead supplying power voltage branches into two adjacent second inner lead portions in one said end portion of said cavity.

Claim 5

The semiconductor integrated circuit according to claim 1, wherein one said branched second inner lead portion has a width larger than an adjacent branched second inner lead portion.

Claim 6

A semiconductor integrated circuit comprising: a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposing end portions and a predetermined internal volume; a plurality of leads, each said lead including an outer lead portion external to said cavity, a first inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width narrower than said first width extending to said semiconductor chip, one of said plurality of leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage having a third width larger than said second width of the second inner lead portions of said plurality of leads adjacent said lead supplying the power voltage; a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; and a dummy lead disposed between said lead supplying the power voltage and another led, said dummy lead having an outer dummy lead portion external to said housing and an inner dummy lead portion having a width equal to the first width, and a termination at one said end portion of said cavity adjacent said housing, wherein the termination of said inner dummy lead provides sufficient area within said housing for said larger third width of the second inner lead portion of said lead supplying the power voltage.

Claim 7

A semiconductor integrated circuit comprising: a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposing end portions and a predetermined internal volume; a plurality of leads, each said lead including an outer lead portion external to said cavity, a first inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width narrower than said first width extending to said semiconductor chip, one of said plurality of leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage having a third width larger than said second width of the second inner lead portions of said plurality of leads adjacent said lead supplying the power voltage; a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; and a dummy lead disposed between said lead supplying the power voltage and another led, said dummy lead having an outer dummy lead portion external to said housing and an inner dummy lead portion having a width equal to the first width, and a termination at one said end portion of said cavity adjacent said housing, wherein the termination of said inner dummy lead provides sufficient area within said housing for said larger third width of the second inner lead portion of said lead supplying the power voltage.

Claim 8

The semiconductor integrated circuit according to claim 5, wherein said dummy inner lead portion connects to a first inner lead portion of an adjacent lead other than the power lead.

Claim 9

A semiconductor integrated circuit a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposite ends and a predetermined internal volume; a plurality of leads, each said lead including an outer lead portion external to said cavity, a first inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width larger than said first width extending to said semiconductor chip, one of said plurality of leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage branching into a plurality of adjacent branched second inner lead portions; a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; a bed centrally located in said plurality of second inner lead portions, for mounting said semiconductor chip in said cavity, said bed having a center and opposing sides; a first suspending pin for supporting said bed extending from one end of said housing to a point on a corresponding side of said bed, offset in a first direction a first distance from a line connecting both opposing sides of said bed extending through said center of said bed; a second suspending pin for supporting said bed extending from the opposite end of said housing to a point on the corresponding opposite side of said bed, offset in a second direction opposite the first direction of second distance equal to the first distance from said line connecting both opposing sides of said bed extending through said center of said bed, wherein the offset portion of said first and second suspending pins provides sufficient area in said housing for said branched second inner lead portions of lead supplying the power voltage.

Claim 10

A semiconductor integrated circuit a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposite ends and a predetermined internal volume; a plurality of leads, each said lead including an outer lead portion external to said cavity, a first inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width larger than said first width extending to said semiconductor chip, one of said plurality of leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage branching into a plurality of adjacent branched second inner lead portions; a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; a bed centrally located in said plurality of second inner lead portions, for mounting said semiconductor chip in said cavity, said bed having a center and opposing sides; a first suspending pin for supporting said bed extending from one end of said housing to a point on a corresponding side of said bed, offset in a first direction a first distance from a line connecting both opposing sides of said bed extending through said center of said bed; a second suspending pin for supporting said bed extending from the opposite end of said housing to a point on the corresponding opposite side of said bed, offset in a second direction opposite the first direction of second distance equal to the first distance from said line connecting both opposing sides of said bed extending through said center of said bed, wherein the offset portion of said first and second suspending pins provides sufficient area in said housing for said branched second inner lead portions of lead supplying the power voltage.

Claim 11

A semiconductor integrated circuit comprising: a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposing end portions and a predetermined internal volume; a plurality of first leads, each said first lead including an outer lead portion external to said cavity, a firt inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width narrower than said first width extending to said semiconductor chip, one of said plurality of first leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage branching into a plurality of adjacent branched second inner lead portions, a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; and a second lead disposed between said lead supplying the power voltage and another adjacent first lead, said second lead including an outer lead portion external to said cavity, and an inner lead portion terminating in an intersection with a first inner lead portion of the adjacent first lead other than the lead supplying the power voltage.

Claim 12

A semiconductor integrated circuit comprising: a semiconductor chip having a surface, including a plurality of pad electrodes fixed to said surface; a housing defining a cavity for housing said semiconductor chip, said cavity having opposing end portions and a predetermined internal volume; a plurality of first leads, each said first lead including an outer lead portion external to said cavity, a firt inner lead portion having a first width adjacent said housing, and a second inner lead portion having a second width narrower than said first width extending to said semiconductor chip, one of said plurality of first leads being a lead supplying a power voltage, and the second inner lead portion of said lead supplying the power voltage branching into a plurality of adjacent branched second inner lead portions, a plurality of metal wires, each said metal wire electrically connecting one said second inner lead portion and one said pad electrode; and a second lead disposed between said lead supplying the power voltage and another adjacent first lead, said second lead including an outer lead portion external to said cavity, and an inner lead portion terminating in an intersection with a first inner lead portion of the adjacent first lead other than the lead supplying the power voltage.