Semiconductor integrated circuit device with an enlarged internal logic circuit area

Claim 2

A semiconductor integrated circuit device, comprising: a semiconductor chip having a central logic circuit area, a peripheral circuit area surrounding said logic circuit area, and bonding pads for interfacing with an external device positioned along edges of said chip in an outer portion of said peripheral circuit area; and a plurality of peripheral circuits formed in said peripheral circuit area inwardly of said bonding pads toward said logic circuit area, said plurality of peripheral circuits having a plurality of N-channel and a plurality of P-channel transistors formed in parallel rows and connected in pairs, each pair including an N-channel and a P-channel transistors each transistor having a largest side portion extending parallel to said chip edge such that each said pair of transistors extends a distance along a periphery of said chip substantially equal to a distance occupied by a plurality of adjacent bonding pads and a distance defined between said adjacent bonding pads formed along said chip edge, wherein a pair of said transistors is connected to form one of a plurality of peripheral circuits, said plurality of peripheral circuits being equal in number to said plurality of adjacent bonding pads, one of said plurality of peripheral circuits being respectively connected to one of said plurality of adjacent bonding pads arranged along said chip edge, wherein a source/drain region of each of said P-channel transistors and N-channel transistors is disposed so that imaginary lines extending from opposite edges of said adjacent bonding pads toward said central logic area cross another imaginary line extending from said source/drain region along the length of each of said P-channel transistors and said N-channel transistors.

Claim 3

A semiconductor integrated circuit device as claimed in claim 1, wherein each said transistor has a largest side portion substantially equal to a peripheral distance of two adjacent bonding pads and a distance defined between said bonding pads, and said transistors are formed as a first group of N-channel transistors and a second group of P-channel transistors, one group being positioned inwardly of the other on said chip, wherein said plurality of peripheral circuits comprises two circuits each composed of at least one pair of transistors.

Claim 4

A semiconductor integrated circuit device as claimed in claim 2, wherein said pair of N-channel and P-channel are arranged side by side in a direction perpendicular to a direction of arrangement of said two adjacent bonding pads.

Claim 5

A semiconductor integrated circuit device as claimed in claim 2, wherein each paired N-channel and P-channel transistor for said two adjacent bonding pads is continuously formed.

Claim 6

A semiconductor integrated circuit device as claimed in claim 2, wherein a width of each said paired N-channel and P-channel transistor is equal to or smaller than a distance between opposite ends of said two bonding pads.

Claim 7

A semiconductor integrated circuit device as claimed in claim 2, wherein said two adjacent bonding pads are separated from each other at a minimum separation distance determined in view of working requirements of wire bonding.

Claim 8

A semiconductor integrated circuit device as claimed in claim 2, wherein each of said peripheral circuits comprises a plurality of pairs of transistors.

Claim 9

A semiconductor integrated circuit device as claimed in claim 1, wherein each pair of transistors is formed in end-to-end relationship parallel to said chip edge, and the combined major dimensions of each pair of transistors is substantially equal to the peripheral distance of three adjacent bonding pads, and wherein said plurality of peripheral circuit comprises three circuits each composed of at least one pair of transistors.

Claim 10

A semiconductor integrated circuit device as claimed in claim 8, wherein said pair of N-channel and P-channel transistors is arranged side by side along the adjacent bonding pads.

Claim 11

A semiconductor integrated circuit device as claimed in claim 8, wherein each of said paired N-channel and P-channel transistors is considerably wider than each of the adjacent bonding pads.

Claim 12

A semiconductor integrated circuit device as claimed in claim 8, wherein a distance between the adjacent bonding pads is larger than a minimum separation distance determined in view of working requirement for wire bonding.

Claim 13

A semiconductor integrated circuit device as claimed in claim 8, wherein the distance between adjacent bonding pads is almost identical to a minimum separation distance determined in view of working requirements for wire bonding.

Claim 14

A semiconductor integrated circuit device as claimed in claim 8, wherein each of said peripheral circuits is composed of a plurality of pairs of transistors.

Claim 15

A semiconductor integrated circuit device as claimed in claim 1, wherein said paired N-channel and P--channel transistors comprise a plurality of source and drain areas alternately arranged in a direction perpendicular to a direction of the arrangement of said bonding pads.

Claim 16

A semiconductor integrated circuit device as claimed in claim 1, wherein said semiconductor integrated circuit device is a master slice type semiconductor integrated circuit device.

Claim 17

A semiconductor integrated circuit device as claimed in claim 15, further comprising a gate electrode provided for each of said N-channel and P-channel transistors, and interconnection lines used for coupling said bonding pads, said P-channel and N-channel transistors, said gate electrodes and said internal logic circuit area.

Claim 18

A semiconductor integrated circuit device as claimed in claim 1, wherein said peripheral circuits comprise an input buffer circuit for buffering a signal supplied from said external device through one of said bonding pads.

Claim 19

A semiconductor integrated circuit device as claimed in claim 1, wherein said peripheral circuits comprise an output buffer circuit for buffering a signal to be outputted to said external device through one of said bonding pads.

Claim 20

A semiconductor integrated circuit device as claimed in claim 1, wherein said peripheral circuits comprise a bi-directional buffer circuit having the function of outputting and inputting a signal to and from said external device.

Claim 21

A semiconductor integrated circuit device as claimed in claim 1, wherein said peripheral circuits comprise a buffer circuit which is provided for each of said plurality of bonding pads and is formed by said pair of N-channel and P-channel transistors.

Claim 22

A semiconductor integrated circuit device, comprising: a semiconductor chip having an internal logic circuit area having internal logic circuits, and a chip peripheral area surrounding said internal logic circuit; a plurality of output electrodes positioned along edges of said semiconductor chip in an outer portion of said chip peripheral area; and a plurality of output circuits for outputting signals supplied from said internal logic circuits to said output electrodes, each of said output circuits including a pair of P-channel transistor and N-channel transistor, one pair of P-channel transistor and N-channel transistor being respectively connected to one of said plurality of output electrodes; wherein each of said output circuits extends a distance along a chip edge of said semiconductor chip substantially equal to a distance occupied by at least two adjacent ones of said output electrodes and a distance defined between said at least two output electrodes arranged along one of said semiconductor chip edges, wherein at least two of said output circuits are arranged between said internal logic circuit area and said at least two adjacent ones of said output electrodes, and wherein a source/drain region of each of said P-channel transistors and N-channel transistors is disposed so that imaginary lines extending from the opposite edges of said adjacent bonding pads toward said central logic area cross another imaginary line extending from said source/drain region along the length of each of said Pl-channel transistors and said N-channel transistors.

Claim 23

A semiconductor integrated circuit device, comprising: a semiconductor chip having an internal logic circuit area having internal logic circuits, and a chip peripheral area surrounding said internal logic circuit; a plurality of output electrodes positioned along edges of said semiconductor chip in an outer portion of said chip peripheral area; and a plurality of output circuits for outputting signals supplied from said internal logic circuits to said output electrodes, each of said output circuits including a pair of P-channel transistor and N-channel transistor, one pair of P-channel transistor and N-channel transistor being respectively connected to one of said plurality of output electrodes; wherein each of said output circuits extends a distance along a chip edge of said semiconductor chip substantially equal to a distance occupied by at least two adjacent ones of said output electrodes and a distance defined between said at least two output electrodes arranged along one of said semiconductor chip edges, wherein at least two of said output circuits are arranged between said internal logic circuit area and said at least two adjacent ones of said output electrodes, and wherein a source/drain region of each of said P-channel transistors and N-channel transistors is disposed so that imaginary lines extending from the opposite edges of said adjacent bonding pads toward said central logic area cross another imaginary line extending from said source/drain region along the length of each of said Pl-channel transistors and said N-channel transistors.

Claim 24

A semiconductor integrated circuit device, comprising: a semiconductor chip having a central logic circuit area, a peripheral circuit area surrounding said logic circuit area, and bonding pads for interfacing with an external device positioned along edges of said chip in an outer portion of said peripheral circuit area; and a plurality of peripheral circuits formed in said peripheral circuit area inwardly of said bonding pads toward said logic circuit area, said plurality of peripheral circuits having a plurality of N-channel and a plurality of P-channel transistors formed in parallel rows and connected in pairs, each pair including an N-channel and a P-channel transistors a distance being defined between said adjacent bonding pads formed along said chip edge, wherein said plurality of bonding pads are aligned substantially parallel to said chip edge, wherein each of said plurality of N-channel transistors and said plurality of P-channel transistors has a length greater than a distance between opposite edges of said adjacent bonding pads and has a channel width smaller than a distance between other edges of said adjacent bonding pads other than said opposite edges of said adjacent bonding pads, wherein a pair of said transistors is connected to form one of a plurality of peripheral circuits, said plurality of peripheral circuits being equal in number to said plurality of adjacent bonding pads, one of said plurality of peripheral circuits being respectively connected to one of said plurality of adjacent bonding pads arranged along said chip edge, and wherein a source/drain region of each of said P-channel transistors and N-channel transistors is disposed so that imaginary lines extending from said opposite edges of said adjacent bonding pads toward said central logic area cross another imaginary line extending from said source/drain region along the length of each of said P-channel transistors and said N-channel transistors.

Claim 25

A semiconductor integrated circuit device, comprising: a semiconductor chip having a central logic circuit area, a peripheral circuit area surrounding said logic circuit area, and bonding pads for interfacing with an external device positioned along edges of said chip in an outer portion of said peripheral circuit area; and a plurality of peripheral circuits formed in said peripheral circuit area inwardly of said bonding pads toward said logic circuit area, said plurality of peripheral circuits having a plurality of N-channel and a plurality of P-channel transistors formed in parallel rows and connected in pairs, each pair including an N-channel and a P-channel transistors a distance being defined between said adjacent bonding pads formed along said chip edge, wherein said plurality of bonding pads are aligned substantially parallel to said chip edge, wherein each of said plurality of N-channel transistors and said plurality of P-channel transistors has a length greater than a distance between opposite edges of said adjacent bonding pads and has a channel width smaller than a distance between other edges of said adjacent bonding pads other than said opposite edges of said adjacent bonding pads, wherein a pair of said transistors is connected to form one of a plurality of peripheral circuits, said plurality of peripheral circuits being equal in number to said plurality of adjacent bonding pads, one of said plurality of peripheral circuits being respectively connected to one of said plurality of adjacent bonding pads arranged along said chip edge, and wherein a source/drain region of each of said P-channel transistors and N-channel transistors is disposed so that imaginary lines extending from said opposite edges of said adjacent bonding pads toward said central logic area cross another imaginary line extending from said source/drain region along the length of each of said P-channel transistors and said N-channel transistors.

Claim 26

A semiconductor integrated circuit device as claimed in claim 22 wherein said P-channel transistors and N-channel transistors form at least one of input and output circuits related to said respective adjacent pads.