Bicmos logic circuit

Claim 2

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a CMOS logic circuit (1) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (5, 6) receiving said input signals; and NPN bipolar transistor (9) having a base connected to said CMOS logic circuit, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said NPN bipolar transistor being driven by an output signal from said CMOS logic circuit; a first N-channel MOSFET (12) having a drain connected to said output terminal and a source connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said higher potential power supply terminal and a gate of said first N-channel MOSFET (12) and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (5, 6) of said CMOS logic circuit; a P-channel MOSFET (11) connected in parallel with said N-channel MOS logic section and receiving at its gate said output signal from said CMOS logic circuit; and a second N-channel MOSFET (10) connected between the gate of said first N-channel MOSFET and said lower potential power supply terminal and receiving at its gate said output signal from said CMOS logic circuit.

Claim 3

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (5a, 6a) receiving said input signals; a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1a) including N-channel MOSFETs (5b, 6b) receiving said input signals; an NPN bipolar transistor (9) having a base connected to said first CMOS logic circuit, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a first N-channel MOSFET (12) having a drain connected to said output terminal and a source connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said higher potential power supply terminal and a gate of said first N-channel MOSFET and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (5a, 6a; 5b, 6b) of said first and second CMOS logic circuits; a P-channel MOSFET (11) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and a second N-channel MOSFET (10) connected between the gate of said first N-channel MOSFET and said lower potential power supply terminal and receiving at its gate said output signal from said second CMOS logic circuit.

Claim 4

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (5a, 6a) receiving said input signals; a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1a) including N-channel MOSFETs (5b, 6b) receiving said input signals; an NPN bipolar transistor (9) having a base connected to said first CMOS logic circuit, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a first N-channel MOSFET (12) having a drain connected to said output terminal and a source connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said higher potential power supply terminal and a gate of said first N-channel MOSFET and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (5a, 6a; 5b, 6b) of said first and second CMOS logic circuits; a P-channel MOSFET (11) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and a second N-channel MOSFET (10) connected between the gate of said first N-channel MOSFET and said lower potential power supply terminal and receiving at its gate said output signal from said second CMOS logic circuit.

Claim 5

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (35a, 36a); a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1b) including N-channel MOSFETs (35b, 35b) receiving said input signals; a first NPN bipolar transistor (39) having a base connected to said first CMOS logic circuit, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said first NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a second NPN bipolar transistor (42) having a collector connected to said output terminal and an emitter connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said output terminal and a base of said second NPN bipolar transistor and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (35a, 36a; 35b, 36b) of said first and second CMOS logic circuits; a P-channel MOSFET (41) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and an N-channel MOSFET (40) connected between the base of said second NPN bipolar transistor and said lower potential power supply terminal and receiving at its gate said output signal from said second CMOS logic circuit.

Claim 6

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (35a, 36a); a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1b) including N-channel MOSFETs (35b, 35b) receiving said input signals; a first NPN bipolar transistor (39) having a base connected to said first CMOS logic circuit, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said first NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a second NPN bipolar transistor (42) having a collector connected to said output terminal and an emitter connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said output terminal and a base of said second NPN bipolar transistor and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (35a, 36a; 35b, 36b) of said first and second CMOS logic circuits; a P-channel MOSFET (41) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and an N-channel MOSFET (40) connected between the base of said second NPN bipolar transistor and said lower potential power supply terminal and receiving at its gate said output signal from said second CMOS logic circuit.

Claim 7

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (35a, 36a) receiving said input signals; a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1b) including N-channel MOSFETs receiving said input signals; a first NPN bipolar transistor (39) having a base connected to said first CMOS logic circuits, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said first NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a second NPN bipolar transistor (42) having a collector connected to said output terminal and an emitter connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said output terminal and a base of said second NPN bipolar transistor and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (35a, 36a; 35b, 36b) of said first and second CMOS logic circuits; a P-channel MOSFET (41) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and an N-channel MOSFET (40) connected between the base of said second NPN bipolar transistor and said lower potential power supply terminal and having its gate connected to said output terminal.

Claim 8

A BiCMOS logic circuit comprising: a higher potential and a lower potential power supply terminal (V DD , GND); a first CMOS logic circuit (1a) for conducting a logical operation on input signals (S 1 , S 2 ) applied thereto and including N-channel MOSFETs (35a, 36a) receiving said input signals; a second CMOS logic circuit (1b) having the same circuit configuration as said first CMOS logic circuit for conducting the same logical operation on said input signals applied thereto, said second CMOS logic circuit (1b) including N-channel MOSFETs receiving said input signals; a first NPN bipolar transistor (39) having a base connected to said first CMOS logic circuits, a collector connected to said higher potential power supply terminal and an emitter connected to an output terminal (T o ), said first NPN bipolar transistor being driven by an output signal from said first CMOS logic circuit; a second NPN bipolar transistor (42) having a collector connected to said output terminal and an emitter connected to said lower potential power supply terminal; an N-channel MOS logic section (2) connected between said output terminal and a base of said second NPN bipolar transistor and having the same circuit configuration and receiving the same input signals as said N-channel MOSFETs (35a, 36a; 35b, 36b) of said first and second CMOS logic circuits; a P-channel MOSFET (41) connected in parallel with said N-channel MOS logic section and receiving at its gate an output signal from said second CMOS logic circuit; and an N-channel MOSFET (40) connected between the base of said second NPN bipolar transistor and said lower potential power supply terminal and having its gate connected to said output terminal.