Semiconductor memory

Claim 1

A semiconductor memory in which a normal memory area is divided into a plurality of divided memory areas for storing data bits, comprising, in combination; a data buffer provided for each of the divided memory areas, the bit lines of each divided memory area being connected via a column selector to a data buffer corresponding to the divided memory area, a buffer changeover switching means connected between each data buffer and the data bus, a column accessing is made by turning on said buffer changeover switching means in a predetermined sequence while said column selector is controlled by output signals of a single column decoder decoding the column address signals, characterized in that said semiconductor memory comprises a redundant memory area for replacing the divided memory area of said normal memory area for a selected bit, a redundant data buffer, redundancy selecting switching means connected between said redundant memory area and said redundant data buffer, redundant data buffer changeover switching means connected between said redundant data buffer and said data bus, bus separating switching means for separating portions corresponding to the normal memory at least during reading, an address comparator circuit for storing the column address of said selected bit and turning said redundancy selecting switching means on when said address and said column address signal coincide with each other, and a redundancy control circuit for turning on said redundant data buffer changeover switching means when the data buffer changeover switching means connected to the data buffer corresponding to the divided memory area of said selected bit is on and the redundancy selecting switching means is on, said control circuit turning said bus separating switching means off and operating said buffer changeover switching means while said column selector is controlled by output signals of said single column decoder decoding the column address signals.