Quantizer and related method for improving linearity

Claim 2

A quantizer circuit, comprising: N analog amplifiers, where N is a positive integer, having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers, where the analog amplifiers are positioned in a sequence corresponding to the values of the analog input reference signals; input means for also coupling the analog input signal to inputs of the analog amplifiers; M threshold circuits for generating a binary output, where M is a positive integer greater than N, said threshold circuits being positioned in a sequence similar to the amplifiers' sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; and analog signal combining means having substantially N inputs and M outputs, which includes a resistor ladder having a first set of tap points that form the input terminals and a second set of tap points that form the output terminals, connected between the analog amplifiers and the threshold circuits, which derive each threshold circuit analog input signal from the weighted sum of the analog outputs of the principal amplifiers and other neighboring amplifiers.

Claim 3

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means which includes a resistor ladder having a first set of tap points that form the input terminals and a second set of tap points that form the output terminals, said signal combining means being connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; and the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs and by adding weighted contributions from others of the N analog inputs.

Claim 4

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means which includes a resistor ladder having a first set of tap points that form the input terminals and a second set of tap points that form the output terminals, said signal combining means being connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; and the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs and by adding weighted contributions from others of the N analog inputs.

Claim 5

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: A plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means, connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a different amplifier which has an emitter-follower output stage, and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M outputs taps, said signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs and by adding weighted contributions from others of the N analog inputs; and the quantizer circuit further comprises substantially 2N coupling resistors connecting the emitter outputs of the emitter follower stages to the resistor ladder, to effect weighted summing of the inputs to the ladder.

Claim 6

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: A plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means, connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a different amplifier which has an emitter-follower output stage, and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M outputs taps, said signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs and by adding weighted contributions from others of the N analog inputs; and the quantizer circuit further comprises substantially 2N coupling resistors connecting the emitter outputs of the emitter follower stages to the resistor ladder, to effect weighted summing of the inputs to the ladder.

Claim 7

A quantizer circuit as defined in claim 3, wherein: the 2N coupling resistors have values greater than the resistance of the resistor ladder segments between adjacent input taps.

Claim 8

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a differential amplifier and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; and the signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs, and by adding weighted contributions from others of the N analog inputs; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps; and the differential amplifiers have their outputs directly coupled to the 2N input taps in the resistor ladder, to effect weighted summing and interpolation of the inputs to the ladder.

Claim 9

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog input signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a differential amplifier and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the threshold circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; and the signal combining means derives each threshold circuit analog input signal from the outputs of one or more principal amplifiers located near the position corresponding to the threshold circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N analog amplifiers and M threshold circuits, where N is less than M and wherein N and M are positive integers; the analog signal combining means has substantially N analog inputs and substantially M analog outputs, and an interpolation function is performed between the outputs of the combining means, wherein an analog output signal on any of the M outputs is derived by interpolating between the closest of the N analog inputs, and by adding weighted contributions from others of the N analog inputs; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps; and the differential amplifiers have their outputs directly coupled to the 2N input taps in the resistor ladder, to effect weighted summing and interpolation of the inputs to the ladder.

Claim 10

A quantizer as defined in claim 5, wherein, the differential amplifier output impedance is greater than the resistance of the resistor ladder segments between adjacent input taps.

Claim 11

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: a plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means, connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a differential amplifier; the signal combining means includes a resistor ladder; the outputs of each differential amplifier are connected to tap points in the resistor ladder; and the resistor ladder generates outputs to the threshold circuits.

Claim 12

A quantizer circuit for converting an analog input signal to a digital output signal, comprising: a plurality of analog amplifiers each having input terminals and output terminals; means for coupling an array of input reference signals to input terminals of the analog amplifiers; input means for also coupling the analog signal to inputs of the analog amplifiers; a plurality of threshold circuits for generating a binary output signal of a given state when an analog input thereto is greater than a predetermined voltage; and signal combining means, connected between the analog amplifiers and the threshold circuits, to receive signals from the output terminals of the amplifiers, and to provide input input signals to the threshold circuits, said signal combining means providing analog inputs to most of the threshold circuits having a voltage level derived from the weighted sum of the outputs from a plurality of the analog amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple analog amplifiers has the effect of improving differential and integral linearity in the event of any component mismatch errors in the analog amplifiers, wherein, each of the amplifiers is a differential amplifier; the signal combining means includes a resistor ladder; the outputs of each differential amplifier are connected to tap points in the resistor ladder; and the resistor ladder generates outputs to the threshold circuits.

Claim 13

A quantizer circuit as defined in claim 7, wherein: there are equal numbers of threshold circuits and amplifiers; and the signal combining means provides an input to threshold circuit n proportional to the sum of the output from amplifier n, and the outputs from other amplifiers multiplied by weighting factors less than unity.

Claim 14

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means including a resistor ladder having a first set of tap points that form the input terminals and a second set of tap points that form the output terminals, said signal combining means connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each thresholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; and the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs.

Claim 15

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means including a resistor ladder having a first set of tap points that form the input terminals and a second set of tap points that form the output terminals, said signal combining means connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each thresholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; and the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs.

Claim 16

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier which has an emitter-follower output stage and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps, said signal combining means derives each thesholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs; and the analog-to-digital converter further comprises substantially 2N coupling resistors connecting the emitter outputs of the emitter follower stages to the resistor ladder, to effect weighted summing of the inputs to the ladder.

Claim 17

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier which has an emitter-follower output stage and said amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps, said signal combining means derives each thesholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs; and the analog-to-digital converter further comprises substantially 2N coupling resistors connecting the emitter outputs of the emitter follower stages to the resistor ladder, to effect weighted summing of the inputs to the ladder.

Claim 18

An analog-to-digital converter as defined in claim 10, wherein: the 2N coupling resistors have values greater than the resistance of the resistor ladder segments between adjacent input taps.

Claim 19

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier and the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each thresholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps; and the differential amplifiers have their outputs directly coupled to the 2N input taps in the resistor ladder, to effect weighted summing and interpolation of the inputs to the ladder.

Claim 20

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier and the amplifiers are positioned in a sequence corresponding to the values of the input reference signals; the thresholding circuits are positioned in a similar sequence, with an amplifier corresponding to a given threshold circuit being referred to as a principal amplifier; the signal combining means derives each thresholding circuit input signal from the outputs of one or more principal amplifiers located near the position corresponding to the thresholding circuit, and from a plurality of other amplifiers located near the principal amplifier; there are N amplifiers and M thresholding circuits, where N is less than M and wherein both N and M are positive integers; the signal combining means has substantially N inputs and M outputs, and an interpolation function is performed between the outputs of the signal combining means, wherein an output signal on any of the M outputs is derived by interpolating between the closest of the N inputs, and by adding weighted contributions from others of the N inputs; the signal combining means includes a resistor ladder having substantially 2N input taps and 2M output taps; and the differential amplifiers have their outputs directly coupled to the 2N input taps in the resistor ladder, to effect weighted summing and interpolation of the inputs to the ladder.

Claim 21

An analog-to-digital converter as defined in claim 12, wherein: the differential amplifier output impedance is greater than the resistance of the resistor ladder segments between adjacent input taps.

Claim 22

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier; the signal combining means includes a resistor ladder; the outputs of each differential amplifier are connected to tap points in the resistor ladder; and the resistor ladder generates outputs to the thresholding circuits from the tap points in the resistor ladder.

Claim 23

An analog-to-digital converter, comprising: a plurality of analog amplifiers each having two input terminals and a plurality of output terminals; a reference signal resistor ladder, to provide an array of input reference signals to a first of the input terminals of the amplifiers; means for coupling an analog input signal to the other of the input terminals of the amplifiers, wherein each amplifier generates a signal indicative of the difference between the analog input signal and an input reference signal corresponding to one of a plurality of reference levels spaced over an analog signal range of interest; a plurality of thresholding circuits for receiving analog input signals and generating quantized signal outputs; signal combining means, connected between the amplifiers and the thresholding circuits, to receive signals from the output terminals of the amplifiers, and to provide input signals to the thresholding circuits, wherein each of the thresholding circuits receives an input signal derived from the weighted sum of the outputs from a plurality of amplifiers operating in a non-saturated mode, whereby summing analog outputs from multiple amplifiers has the effect of improving differential and integral linearity in the event of any amplifier offset errors; and a decoder to receive converted signals from most of the analog-to-digital thresholding circuits and to generate therefrom a digital signal indicative of the magnitude of the analog input signal, wherein, each of the amplifiers is a differential amplifier; the signal combining means includes a resistor ladder; the outputs of each differential amplifier are connected to tap points in the resistor ladder; and the resistor ladder generates outputs to the thresholding circuits from the tap points in the resistor ladder.

Claim 24

An analog-to-digital converter as defined in claim 14, wherein: there are equal numbers of thresholding circuits and amplifiers; and the signal summing means provides an input to thresholding circuit n proportional to the sum of the output from amplifier n, and the outputs from other amplifiers multiplied by weighting factors less than unity.