Parallel analog-to-digital converter using 2.sup.(n-1) comparators

Claim 1

An analog-to digital flash converter for converting an analog signal to an n-bit digital signal, said converter comprising: 2 n /2 consecutive input comparators, each having a first input coupled to receive said analog signal, means for producing 2 n /2 reference voltages spaced apart by two LSBs of said converter and for providing one each of said 2 n /2 reference voltages to a second input of each input comparator, each of said input comparators having first and second outputs, said first output generally being at a first voltage level when said analog signal is greater than the associated reference signal and at a second voltage level when said analog signal is less than the associated reference signal and said first output gradually transitioning from said first output voltage level to said second output voltage level where said analog signal and said associated reference signal are approximately equal, and said second output being the inverse of said first output, and 2 n /2 latch means, each associated with one of said input comparators and having first and second inputs for accepting said first and second outputs of said associated input comparator, (2 n /2)-1 additional latch means, each additional latch means having a first input coupled to receive said first output of one of said input comparators and a second input coupled to receive said second output of an input comparator adjacent said one of said input comparators, said latch means and additional latch means each having an output which is of a first latch output voltage when said first input thereto is less than said second input thereto and of a second latch output voltage when said first input thereto is greater than said second input thereto.