Parallel comparison type analog to digital converter

Claim 2

A parallel comparison analog to digital converter comprising: a voltage dividing circuit for generating a plurality of ordered comparison voltages; and equal plurality of ordered comparison circuits for comparing said plurality of voltages, respectively, with a common analog input voltage to be digitally converted; a position detecting circuit responsive to the outputs of said plurality of comparison circuits for developing a digital output dependent upon the order of the crossover between those comparison circuits which receive a lower comparison voltage than said common analog input voltage and those comparison circuits which receive a higher comparison voltage than said common analog input voltage; said comparison circuits being of the type which produce a first binary level output when said analog input voltage is sufficiently above said comparison voltage, a second binary level output when said analog input voltage is sufficiently below said comparison voltage, and an intermediate level output when said analog input is neither sufficiently above nor sufficiently below said comparison voltage, said position detecting circuit having an equal plurality of ordered logic gates, each having a first input means adapted to receive an output of the comparison circuit of the same order and a second input means adapted to receive an output of the comparison circuit of the preceding order, said first input means having a first logic threshold value which is lower than said intermediate level output and being adapted to recognize the intermediate level output as a first binary level output, said second input means having a second logic threshold value which is above said intermediate level output and being adapted to recognize the intermediate level output as a second binary level output.

Claim 3

A parallel comparison analog to digital converter as claimed in claim 1, wherein each of said logic gates includes an AND gate receiving by the first input means the output from the comparison circuit of the same order, each of said AND gates having said first logic threshold value.

Claim 4

A parallel comparison analog to digital converter as claimed in claim 2, wherein said second input means includes an inverter stage having its output connected to a second input of the AND gate of the same order, each inverter stage, except for the first in the order of inverter gates, having its input connected to the output of the comparison circuit of the preceding order by one, each of said inverter gates having said second logic threshold value.

Claim 5

A parallel comparison analog to digital converter as claimed in claim 3, wherein the output of each comparison circuit, except for the first comparison circuit in the order, is applied to a third input of the AND gate which precedes it by one in the order.

Claim 6

A parallel comparison analog to digital converter as claimed in claim 1, wherein each of said first input means includes an inverter gate having as its input the output from the comparison circuit of the same order, said inverter gate having said first logic threshold value.

Claim 7

A parallel comparison analog to digital converter as claimed in claim 5, wherein each of said logic gates includes a NOR gate having a first input connected to the output of the inverter gate of the same order, each said NOR gate, except for the first of said order, having a second input connected to the output of the comparison circuit which precedes it by one in the order, wherein each said NOR gate serves as said second input means having said second logic threshold.

Claim 8

A parallel comparison analog to digital converter as claimed in claim 6, wherein each inverter gate, except for the first in the order, has its output connected to a third input of the NOR gate which precedes it by one in the order.

Claim 9

A parallel comparison analog to digital converter, comprising: a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator, said comparators producing either one of two binary logic levels when a difference between the analog signal and the comparison voltage applied thereto is relatively large and producing an intermediate level between the two binary logic levels when the difference between the analog signal and the comparison voltage is relatively small; a position detecting circuit coupled to said comparators for digitizing a value of said analog signal, said position detecting circuit including a plurality of logic gates each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precedes the gate by one in the order, the logic gate distinguishing the signal applied to the first input terminal thereof into one of the binary logic levels at a first threshold value and distinguishing the signal applied to the second input terminal thereof into one of the binary logic levels at a second threshold value different from said first threshold value, said first and second threshold values being determined in such manner that said intermediate level lies between said first and second threshold levels, wherein the output of said intermediate level from the comparator of a certain order is set at one of the binary logic levels for the first input terminal of the logic gate of said certain order and set at the other of the binary logic levels for the second input terminal of the logic gate of the order which precedes said certain order by one.

Claim 10

A parallel comparison analog to digital converter, comprising: a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator, said comparators producing either one of two binary logic levels when a difference between the analog signal and the comparison voltage applied thereto is relatively large and producing an intermediate level between the two binary logic levels when the difference between the analog signal and the comparison voltage is relatively small; a position detecting circuit coupled to said comparators for digitizing a value of said analog signal, said position detecting circuit including a plurality of logic gates each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precedes the gate by one in the order, the logic gate distinguishing the signal applied to the first input terminal thereof into one of the binary logic levels at a first threshold value and distinguishing the signal applied to the second input terminal thereof into one of the binary logic levels at a second threshold value different from said first threshold value, said first and second threshold values being determined in such manner that said intermediate level lies between said first and second threshold levels, wherein the output of said intermediate level from the comparator of a certain order is set at one of the binary logic levels for the first input terminal of the logic gate of said certain order and set at the other of the binary logic levels for the second input terminal of the logic gate of the order which precedes said certain order by one.

Claim 11

The converter according to claim 8, in which each of said gates includes an AND gate having a first input terminal and a second input terminal and an inverter having an output coupled to the second input terminal of said AND gate, said first input terminal and the input of said AND gate serving as said first logic input terminal and the input of said inverter serving as said second logic input terminal.

Claim 12

The converter according to claim 8, in which each of said logic gates includes a NOR circuit having first and second input terminals, and an inverter having an output coupled to said first input terminal of said NOR circuit, said second input terminal of said NOR circuit serving as said second logic input terminal of said logic gate, the input terminal of said inverter serving as said first logic input terminal of said logic gate.

Claim 13

The converter according to claim 8, in which said voltage dividing circuit includes a plurality of resistors connected in series between two different voltages.

Claim 14

The converter according to claim 8, in which said decoder circuit includes a read only memory circuit storing Gray code data and a conversion circuit coupled to said read only memory circuit for converting the output of said read only memory circuit to a regular binary coded signal.

Claim 15

A parallel comparison analog to digital converter comprising: a voltage dividing circuit for generating a plurality of ordered comparison voltages; an equal plurality of ordered comparison circuits for comparing said plurality of voltages, respectively, with a common analog input voltage to be digitally converter; a position detecting circuit responsive to the outputs of said plurality of comparison circuits for developing a digital output dependent upon the order of the crossover between those comparison circuits which receive a lower comparison voltage than said common analog input voltage and those comparison circuits which receive a higher comparison voltage than said common analog input voltage, said comparison circuits being of the type which produce a first binary level output when said analog input voltage is sufficiently above said comparison voltage, a second binary level output when said analog input voltage is sufficiently below said comparison voltage, and an intermediate level output when said analog input is neither sufficiently above nor sufficiently below said comparison voltage; the improvement comprising: first logic circuit means in said position detecting circuit having a first binary threshold level below said intermediate level and second logic circuit means in said position detecting circuit having a second binary threshold level above said intermediate level; said first logic circuit means including an ordered plurality of inverter gates, each inverter gate having as its input the output from the comparison circuit of the same order and the input terminal of each said inverter gate having a threshold level at which the gate distinguishes between a "0" and a "1" at said first binary threshold level; and said logic circuit means comprises an ordered plurality of NOR gates, each said NOR gate having a first input connected to the output of the inverter gate of the same order, each said NOR gate, except for the first of said order, having a second input connected to the output of the comparison circuit which precedes it by one in the order and the input terminals of each said NOR gate having a threshold level at which the gate distinguishes between a "0" and a "1" at said second binary threshold level.

Claim 16

A parallel comparison analog to digital converter comprising: a voltage dividing circuit for generating a plurality of ordered comparison voltages; an equal plurality of ordered comparison circuits for comparing said plurality of voltages, respectively, with a common analog input voltage to be digitally converter; a position detecting circuit responsive to the outputs of said plurality of comparison circuits for developing a digital output dependent upon the order of the crossover between those comparison circuits which receive a lower comparison voltage than said common analog input voltage and those comparison circuits which receive a higher comparison voltage than said common analog input voltage, said comparison circuits being of the type which produce a first binary level output when said analog input voltage is sufficiently above said comparison voltage, a second binary level output when said analog input voltage is sufficiently below said comparison voltage, and an intermediate level output when said analog input is neither sufficiently above nor sufficiently below said comparison voltage; the improvement comprising: first logic circuit means in said position detecting circuit having a first binary threshold level below said intermediate level and second logic circuit means in said position detecting circuit having a second binary threshold level above said intermediate level; said first logic circuit means including an ordered plurality of inverter gates, each inverter gate having as its input the output from the comparison circuit of the same order and the input terminal of each said inverter gate having a threshold level at which the gate distinguishes between a "0" and a "1" at said first binary threshold level; and said logic circuit means comprises an ordered plurality of NOR gates, each said NOR gate having a first input connected to the output of the inverter gate of the same order, each said NOR gate, except for the first of said order, having a second input connected to the output of the comparison circuit which precedes it by one in the order and the input terminals of each said NOR gate having a threshold level at which the gate distinguishes between a "0" and a "1" at said second binary threshold level.

Claim 17

A parallel comparison analog to digital converter as claimed in claim 13, wherein said first binary threshold level is lower than said second binary threshold level.

Claim 18

A parallel comparison analog to digital converter as claimed in claim 13, wherein each inverter gate, except for the first in the order, has its output connected to a third input of the NOR gate which precedes it by one in the order.

Claim 19

A parallel comparison type analog to digital converter comprising: a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator; a position detection circuit coupled to said comparators for digitizing a value of said analog signal, said position detecting circuit including a plurality of logic gates, each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precede the gate by one in the order, the threshold values of said first and second logic input terminals being different from each other, and a decoder circuit for generating a digital output in response to the output of said position detecting circuit, wherein each of said logic gates includes a NOR circuit, having a first and second input terminals, and an inverter, having an output coupled to said first input terminal of said NOR circuit, said second input terminal of said NOR circuit serves as said second logic input terminal of said logic gate and the input terminal of said inverter serves as said first logic input terminal of said logic gate.

Claim 20

A parallel comparison type analog to digital converter comprising: a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator; a position detection circuit coupled to said comparators for digitizing a value of said analog signal, said position detecting circuit including a plurality of logic gates, each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precede the gate by one in the order, the threshold values of said first and second logic input terminals being different from each other, and a decoder circuit for generating a digital output in response to the output of said position detecting circuit, wherein each of said logic gates includes a NOR circuit, having a first and second input terminals, and an inverter, having an output coupled to said first input terminal of said NOR circuit, said second input terminal of said NOR circuit serves as said second logic input terminal of said logic gate and the input terminal of said inverter serves as said first logic input terminal of said logic gate.

Claim 21

A parallel comparison type analog to digital converter comprising: means for receiving an analog signal; a voltage generation circuit for generating a plurality of comparison voltages of different values; a plurality of comparator circuits, each having a first input terminal receiving said analog signal and a second input terminal receiving an associated one of said comparison voltages, each of said comparator circuits being weighted in an ordered sequence by the comparison voltage applied thereto; a plurality of logic gates, each having a first logic input terminal receiving an output signal from an associated one of said comparator circuits and a second logic input terminal receiving an output signal from the comparator circuit having the weighting subsequent to that of said associated one of said comparator circuits, each of said logic gates generating an active level output when said first input logic input terminal thereof is at a first logic level and said second logic input terminal thereof is at a second logic level, the threshold values of said first and second logic input terminals of said logic gates being made different from each other; and a decoder circuit coupled to the output of said logic gates for generating a digital output, wherein each of said logic gates includes a NOR circuit, having a first input terminal and a second input terminal, and an inverter circuit, having an output connected to the first input terminal of said NOR circuit, said inverter circuit having an input terminal serving as said first logic input terminal, the second input terminal of said NOR circuit serving as said second logic input terminal, and a threshold value of said inverter circuit being made lower than that of said NOR circuit.

Claim 22

A parallel comparison type analog to digital converter comprising: means for receiving an analog signal; a voltage generation circuit for generating a plurality of comparison voltages of different values; a plurality of comparator circuits, each having a first input terminal receiving said analog signal and a second input terminal receiving an associated one of said comparison voltages, each of said comparator circuits being weighted in an ordered sequence by the comparison voltage applied thereto; a plurality of logic gates, each having a first logic input terminal receiving an output signal from an associated one of said comparator circuits and a second logic input terminal receiving an output signal from the comparator circuit having the weighting subsequent to that of said associated one of said comparator circuits, each of said logic gates generating an active level output when said first input logic input terminal thereof is at a first logic level and said second logic input terminal thereof is at a second logic level, the threshold values of said first and second logic input terminals of said logic gates being made different from each other; and a decoder circuit coupled to the output of said logic gates for generating a digital output, wherein each of said logic gates includes a NOR circuit, having a first input terminal and a second input terminal, and an inverter circuit, having an output connected to the first input terminal of said NOR circuit, said inverter circuit having an input terminal serving as said first logic input terminal, the second input terminal of said NOR circuit serving as said second logic input terminal, and a threshold value of said inverter circuit being made lower than that of said NOR circuit.