Parallel analog-to-digital converter

Claim 1

In a parallel analog-to-digital converter with p=2 r -1 comparators, where r is the number of bits of the (r+1)-bit converter output signal diminished by 1, and the analog signal is applied to either the noninverting or inverting input of each comparator and the other of said comparator inputs being connected consecutively to the taps of a resistive voltage divider consisting of equal-value resistors and having a reference voltage (Ur) applied thereto, wherein the analog signal is shifted by ΔU=Ur/2 r+1 for the duration of every second clock period of the converter clock signal, and wherein the comparator outputs are connected to a digital encoder followed by a buffer memory, wherein the improvement comprises: a pair of transistors having their emitters connected; a resistor connected between the collectors of the two transistors, with the analog signal being applied to the appropriate comparator inputs through said resistor; a constant current source disposed in the emitter path of the pair of transistors, the base of one of the transistors being supplied with a fixed potential, and the base of the other transistor being fed with a clock signal having one-half the frequency of the converter clock signal, the value of the resistor being chosen in accordance with the equation R=ΔU/I=2 - (r+1) Ur/I, where I is the strength of the constant current source; and an exclusive-OR gate having inputs being provided with the least significant bit at the output of the digital encoder and the corresponding bit at the output of the buffer memory, whereby the gate output provides a signal that functions as the least significant bit of the output signal of the parallel analog-to-digital converter.