Parallel analog-to-digital converter

Claim 2

An A-to-D converter comprising an electronic comparator for comparing an analog input signal with each of a number of discrete level reference signal inputs, said comparator having a one bit binary output, the value of which alternates as the analog signal increases to successively exceed said reference signal levels, said comparator comprising: a pair of differential transistors associated with each reference input, the base of a reference transistor of each pair being connected to the associated reference input and the base of an input transistor of each pair being connected to the analog input signal; first common connector means for connecting the outputs of the reference transistors of a first set of transistor pairs associated with a first set of non-successive reference inputs in common with each other and with the outputs of the input transistors of a second set of transistor pairs associated with a second set of non-successive reference inputs; second common connector means for connecting the outputs of the reference transistors of said secnd set of transistor pairs in common with each other and with the outputs of the input transistors of said first set of transistor pairs; differential transistor bias means for drawing predetermined amounts of current through each of said pairs of differential transistors, the portions of said predetermined amounts of current drawn through each transistor of each pair being determined by the level of said analog input signal relative to said associated reference input; and means for detecting the amount of current drawn through said first common connector means relative to the current drawn through said second common connector means, whereby the relative currents through said connector means indicates said one bit binary output.

Claim 3

The electronic comparator as claimed in claim 1 wherein each pair of differential transistors comprises a pair of common emitter transistors and the collectors of successive pairs of differential transistors are cross coupled to said first and second common connector means.

Claim 4

The electronic comparator as claimed in claim 1 further comprising a latching circuit coupled to said first and second common connector means and operable regeneratively to reinforce conditions established in said connector means by a small current unbalance when the analog signal is close to the value of the corresponding reference signal.

Claim 5

The electronic comparator as claimed in claim 1 wherein said differential transistor bias means comprises a separate bias transistor associated with each pair of differential transistors, the bases of said bias transistors being connected in common so that equal amounts of current are drawn through said pairs of differential transistors.

Claim 6

An A-to-D converter comprising an electronic comparator and exclusive-OR logic gate for comparing an analog input signal with each of a number of discrete level reference signal inputs, said comparator having a one bit binary output the value of which alternates as the analog signal increases to successively exceed said reference signal levels, and for combining said one bit binary output with a second one bit binary signal according to an exclusive-OR function, said comparator and exclusive-OR gate comprising: a pair of differential transistors associated with each reference input, the base of a reference transistor of each pair being connected to the associated reference input and the base of an input transistor of each pair being connected to the analog input signal; first common connector means for connecting the outputs of the reference transistors of a first set of transistor pairs associated with a first set of non-successive reference inputs in common with each other and with the outputs of the input transistors of a second set of transistor pairs associated with a second set of non-successive reference inputs; second common connector means for connecting the outputs of the reference transistors of said second set of transistor pairs in common with each other and with the outputs of the input transistors of said first set of transistor pairs; differential transistor bias means for drawing predetermined amounts of current through each of said pairs of differential transistors, the portions of said predetermined amounts of current drawn through each transistor of each pair being determined by the level of said analog input signal relative to said associated reference input; a first gate differential transistor pair connected to detect the amount of current drawn through said first common connector means and a second gate differential transistor pair connected to detect the amount of current drawn through said second common connector means; means for applying a common bias voltage to one transistor of each of said gate differential transistor pairs; means for applying said other one bit binary signal to the bases of the other transistors of said gate differential transistor pairs; means for cross coupling the outputs of said gate differential transistor pairs to two gate outputs; and means for detecting the relative values of said two gate outputs.

Claim 7

An A-to-D converter comprising an electronic comparator and exclusive-OR logic gate for comparing an analog input signal with each of a number of discrete level reference signal inputs, said comparator having a one bit binary output the value of which alternates as the analog signal increases to successively exceed said reference signal levels, and for combining said one bit binary output with a second one bit binary signal according to an exclusive-OR function, said comparator and exclusive-OR gate comprising: a pair of differential transistors associated with each reference input, the base of a reference transistor of each pair being connected to the associated reference input and the base of an input transistor of each pair being connected to the analog input signal; first common connector means for connecting the outputs of the reference transistors of a first set of transistor pairs associated with a first set of non-successive reference inputs in common with each other and with the outputs of the input transistors of a second set of transistor pairs associated with a second set of non-successive reference inputs; second common connector means for connecting the outputs of the reference transistors of said second set of transistor pairs in common with each other and with the outputs of the input transistors of said first set of transistor pairs; differential transistor bias means for drawing predetermined amounts of current through each of said pairs of differential transistors, the portions of said predetermined amounts of current drawn through each transistor of each pair being determined by the level of said analog input signal relative to said associated reference input; a first gate differential transistor pair connected to detect the amount of current drawn through said first common connector means and a second gate differential transistor pair connected to detect the amount of current drawn through said second common connector means; means for applying a common bias voltage to one transistor of each of said gate differential transistor pairs; means for applying said other one bit binary signal to the bases of the other transistors of said gate differential transistor pairs; means for cross coupling the outputs of said gate differential transistor pairs to two gate outputs; and means for detecting the relative values of said two gate outputs.

Claim 8

The electronic comparator as claimed in claim 5 wherein each pair of differential transistors comprises a pair of common emitter transistors and the collectors of successive pairs of differential transistors are cross coupled to said first and second common connector means.

Claim 9

The electronic comparator as claimed in claim 5 further comprising a latching circuit coupled to said first and second common connector means and operable regeneratively to reinforce conditions established in said connector means by a small current unbalance when the analog signal is close to the value of the corresponding reference signal.

Claim 10

The electronic comparator as claimed in claim 5 wherein said differential transistor bias means comprises a separate bias transistor associated with each pair of differential transistors, the bases of said bias transistors being connected in common so that equal amounts of current are drawn through said pairs of differential transistors.

Claim 11

In a parallel analog-to digital converter of the type having an input circuit to receive an analog input signal, a plurality of comparators connected in common to said circuit with each providing one bit of the digital output signal, and wherein the value of such bit alternates as the input analog signal varies through its range of variation; that improvement wherein at least one of said comparators comprises: reference circuit means establishing a plurality of discrete predetermined fixed progressive-valued reference signal levels; a plurality of voltage comparison circuit means each having an input terminal and a reference terminal; means connecting all of said input terminals in common to said input circuit to receive the analog signal applied thereto; means connecting said reference signal levels to respective reference terminals of said plurality of voltage-comparison circuit means; said plurality of voltage comparison circuit means each including output circuit means electrically isolated from said reference circuit means and operable to produce a comparison signal having a level determined by whether the input terminal or the reference terminal of that voltage-comparison circuit means receives the higher signal level; said isolation of said reference circuit means providing for maintenance of said predetermined reference signal levels independent of alteration of the value of any of the comparison signals; offset means coupled to said plurality of voltage comparison circuit means to provide thereto a predetermined bias signal; and combining means coupled to all of said output circuit means and including means responsive to all or said comparison signals and said bias signal to develop a composite binary output signal having a net value determined by the net values of all of said comparison signals.

Claim 12

In a parallel analog-to digital converter of the type having an input circuit to receive an analog input signal, a plurality of comparators connected in common to said circuit with each providing one bit of the digital output signal, and wherein the value of such bit alternates as the input analog signal varies through its range of variation; that improvement wherein at least one of said comparators comprises: reference circuit means establishing a plurality of discrete predetermined fixed progressive-valued reference signal levels; a plurality of voltage comparison circuit means each having an input terminal and a reference terminal; means connecting all of said input terminals in common to said input circuit to receive the analog signal applied thereto; means connecting said reference signal levels to respective reference terminals of said plurality of voltage-comparison circuit means; said plurality of voltage comparison circuit means each including output circuit means electrically isolated from said reference circuit means and operable to produce a comparison signal having a level determined by whether the input terminal or the reference terminal of that voltage-comparison circuit means receives the higher signal level; said isolation of said reference circuit means providing for maintenance of said predetermined reference signal levels independent of alteration of the value of any of the comparison signals; offset means coupled to said plurality of voltage comparison circuit means to provide thereto a predetermined bias signal; and combining means coupled to all of said output circuit means and including means responsive to all or said comparison signals and said bias signal to develop a composite binary output signal having a net value determined by the net values of all of said comparison signals.

Claim 13

Apparatus as in claim 9, comprising a plurality of current generators each coupled to a respective voltage comparison circuit means to control the corresponding output current thereof to a predetermined magnitude.

Claim 14

Apparatus as in claim 9, wherein said offset means comprises a current generator directing a bias current of a predetermined level to said output circuit means.

Claim 15

Apparatus as in claim 9, wherein each of said comparison circuit means comprises first and second output terminals and differential means to produce a differential comparison signal at said first and second output terminals; said combining means comprising first and second output leads; means connecting all of said first output terminals in common to said first output lead; and means connecting all of said second output terminals in common to said second output lead.

Claim 16

A converter as claimed in claim 12, wherein said comparison circuits comprise a pair of transistors; means connecting the emitters of each transistor pair together; means connecting the collectors of each pair to said first and second output leads respectively; means connecting the base of one transistor of each pair to said input terminal; and means connecting the base of the other transistor of each pair to the respective reference signal level.

Claim 17

A converter as claimed in claim 13, including current sink means connected to said emitters to control the current level flowing through one or the other collector in accordance with the relative values of the corresponding input and reference signals.

Claim 18

A converter as claimed in claim 12, including latching means connected to said first and second output leads and including regenerative means responsive to the relative signal levels on said two leads for locking in the binary value as the input signal applied to any of said comparison circuits is close to equality with the corresponding reference signal level.

Claim 19

A converter as claimed in claim 15, wherein said latching means comprises two transistors having their bases connected respectively to said first and second output leads and their collectors cross-coupled respectively to said first and second output leads; means connecting the emitters of said two transistors together; current control means coupled to said emitters to provide a predetermined current flow from the emitters; and clock means coupled to said latching means to time the operation thereof in accordance with clock pulses.

Claim 20

A converter as claimed in claim 12, wherein each of said comparison circuits comprises differentially-operable means for alternatively developing a comparison signal for one or the other of said first and second output leads in accordance with whether said input signal or the corresponding reference signal is the higher; and a balanced exclusive-OR circuit connected to said first and second output leads and responsive to the bit output from another of said comparators to develop the digital bit output for one of said comparators.

Claim 21

A converter as claimed in claim 17, wherein said exclusive-OR circuit comprises two pairs of transistors wherein the emitters of each pair are connected together and to a respective one of said output leads; the bases of one transistor of each of said pairs of transistors being connected together and to a terminal receiving said bit output of said other comparator; the bases of the other transistors of said pairs of transistors being connected together and to a reference voltage; and means connected to the collectors of said two pairs of transistors for producing said digital bit output for one of said comparators.