Transient recorder

Claim 2

Apparatus for recording a plurality of points of an input analog signal in response to a command signal comprising: analog-to-digital converter means for providing a digital code signal having n-bit words corresponding to points of said input signal, memory means for storing w n-bit digital code signal words, where w is a positive integer, means responsive to said command signal for reading said digital code signal into said memory means at a first rate, and means responsive to a further command signal for recirculating stored digital code words in said memory means.

Claim 3

Apparatus according to claim 1 further comprising: means for generating a trigger signal and for applying said trigger signal as said command signal to said memory means read in means; and means for selectively delaying said trigger signal for a time of zero or greater.

Claim 4

the variable Xyz changes from '''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z < or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 5

the variable Xyz changes from '''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z < or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 6

the variable Xyz changes from ''''0'''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z > or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 7

the variable Xyz changes from ''''0'''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z > or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 8

the variable Xyz changes from ''''0'''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z > or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 9

the variable Xyz changes from ''''0'''' to ''''1'''' at transition (voltage sensing level) z; 1 < or = z < or = 2n 1 and Xyz ''''0'''' for z > or = 2n 1, Xyz corresponding to the signal at each reference level and Xyz corresponding to the complement of the voltage at each reference level;

Claim 10

Qy value of the desired output code (for column y) between transition Xyz and Xy(z 2y); and

Claim 11

Qy value of the desired output code (for column y) between transition Xyz and Xy(z 2y); and

Claim 12

Qy value of the desired output code (for column y) between transition Xyz and Xy(z 2 ); and

Claim 13

Qy value of the desired output code (for column y) between transition Xyz and Xy(z 2 ); and

Claim 14

Qy value of the desired output code (for column y) between transition Xyz and Xy(z + 2y); and

Claim 15

Qy value of the desired output code (for column y) between transition Xyz and Xy(z + 2y); and

Claim 16

Apparatus according to claim 2 wherein said trigger signal is generated in response to an external signal.

Claim 17

Apparatus according to claim 2 wherein said trigger signal is generated internally in response to a predetermined point on said analog signal, said trigger signal occurring repetetively in response to a cyclic input signal.

Claim 18

z'' voltage sensing level at which the first transition occurs in column y.

Claim 19

z'' voltage sensing level at which the first transition occurs in column y.

Claim 20

z'' voltage sensing level at which the first transition occurs in column y. f. connecting the voltage sensing levels according to the defined logic relationship.

Claim 21

z'' voltage sensing level at which the first transition occurs in column y. f. connecting the voltage sensing levels according to the defined logic relationship.

Claim 22

z'' voltage sensing level at which the first transition occurs in column y.

Claim 23

z'' voltage sensing level at which the first transition occurs in column y.

Claim 24

Apparatus according to claim 2 wherein said trigger signal is generated internally in response to the first occurrence of a predetermined point on said input analog signal.

Claim 25

Apparatus according to claim 1 further comprising: means operable in a pre-trigger mode of said apparatus for applying said command signal and said further command signal to initially continuously recirculate and update stored digital code words in said memory means; and means responsive to a predetermined point on said analog input signal for interrupting said further command signal to stop recirculation of code words in said memory means.

Claim 26

Apparatus according to claim 6 further comprising means for selectively delaying the interruption of said further command signal.

Claim 27

Apparatus according to claim 1 wherein said apparatus is further for reading out said recorded signal, said apparatus further comprising: means for selectively reading said digital code words out of said memory means at a second rate slower than said first rate.

Claim 28

Apparatus according to claim 6 wherein said apparatus is further for reading out said recorded signal, said apparatus further comprising: means for selectively reading said digital code words out of said memory means at a second rate slower than said first rate.

Claim 29

Apparatus for recording an input analog signal using a digital code having n-bit words wherein each bit column of said code has an assigned value y 1,2,3 . . . n in descending order in accordance with the number of level transitions in the bit column, each bit column having 2n y transitions and 2y spaces between transitions, comprising: analog-to-digital converter means for providing a digital code signal having n-bit words in response to said input signal; memory means receiving said digital code Signal for storing w n-bit words of said code, where w is a positive integer; said analog to digital converter means comprising: means for simultaneously comparing said signal with reference voltages at z 2n-1 discrete voltage levels; means for generating a signal having a first polarity representative of 1 at each reference level at which said signal exceeds said reference voltage and having a second polarity representative of 0 at each reference level at which said reference level exceeds said signal; means for generating the complement of said signal at each reference level; means for connecting said first and second polarity signals and said first and second polarity signal complements according to the relationship:

Claim 30

Apparatus for recording an input analog signal using a digital code having n-bit words wherein each bit column of said code has an assigned value y 1,2,3 . . . n in descending order in accordance with the number of level transitions in the bit column, each bit column having 2n y transitions and 2y spaces between transitions, comprising: analog-to-digital converter means for providing a digital code signal having n-bit words in response to said input signal; memory means receiving said digital code Signal for storing w n-bit words of said code, where w is a positive integer; said analog to digital converter means comprising: means for simultaneously comparing said signal with reference voltages at z 2n-1 discrete voltage levels; means for generating a signal having a first polarity representative of 1 at each reference level at which said signal exceeds said reference voltage and having a second polarity representative of 0 at each reference level at which said reference level exceeds said signal; means for generating the complement of said signal at each reference level; means for connecting said first and second polarity signals and said first and second polarity signal complements according to the relationship:

Claim 31

Apparatus according to claim 10 wherein said analog-to-digital converter means further comprises means for sensing the current variations in said voltage sensing levels associated with said bit column for which y 1, means for generating current sense signal of a first polarity when said current variations fall within two predetermined levels and for generating a signal of a second polarity when said current variations fall outside said levels.

Claim 32

Apparatus for converting an analog signal waveform to digital form and for storing said digital signal in a memory during a record mode of operation and for reading out said digital signal from said memory during a playback mode of operation comprising a. triggering means receiving said analog signal for generating a trigger pulse at predetermined point on the wave form of said signal, b. means for providing an adjustable rate clock signal, c. analog-to-digital converter means receiving said analog signal for converting said signal to cyclic digital code words of x-bit length. d. memory means for storing w digital code words of n-bit length in a recirculating format said memory having 1 through w discrete word addresses, at least one of said addresses being available for reading in or reading out a code word at a particular time, e. memory tracking counter means for indicating the address of the code word available at said memory means, f. interlace index counter means for indicating the memory means address at which the next code word is to be read-in or read-out, g. means for comparing addresses of said memory tracking counter means and said interlace index counter means for generating a coincidence pulse upon coincidence of said addresses, h. control logic means receiving said clock pulses, said trigger pulses, and said coincidence pulses for providing read-in and read-out pulses, i. input buffer register means receiving said digital code words from said converter means and said read-in pulses for reading in a code word to said memory means upon receipt of a read in pulse, j. output buffer register means for reading out a code word from said memory upon receipt of a read-out pulse,

Claim 33

Apparatus for converting an analog signal waveform to digital form and for storing said digital signal in a memory during a record mode of operation and for reading out said digital signal from said memory during a playback mode of operation comprising a. triggering means receiving said analog signal for generating a trigger pulse at predetermined point on the wave form of said signal, b. means for providing an adjustable rate clock signal, c. analog-to-digital converter means receiving said analog signal for converting said signal to cyclic digital code words of x-bit length. d. memory means for storing w digital code words of n-bit length in a recirculating format said memory having 1 through w discrete word addresses, at least one of said addresses being available for reading in or reading out a code word at a particular time, e. memory tracking counter means for indicating the address of the code word available at said memory means, f. interlace index counter means for indicating the memory means address at which the next code word is to be read-in or read-out, g. means for comparing addresses of said memory tracking counter means and said interlace index counter means for generating a coincidence pulse upon coincidence of said addresses, h. control logic means receiving said clock pulses, said trigger pulses, and said coincidence pulses for providing read-in and read-out pulses, i. input buffer register means receiving said digital code words from said converter means and said read-in pulses for reading in a code word to said memory means upon receipt of a read in pulse, j. output buffer register means for reading out a code word from said memory upon receipt of a read-out pulse,

Claim 34

Apparatus according to claim 12 further comprising means receiving said read-out code word for converting said cyclic digital code word to a binary digital code word.

Claim 35

Apparatus according to claim 13 further comprising digital-to-analog converter means receiving said binary code word for converting said code word to an analog signal.

Claim 38

Apparatus for generating a digital code having two levels and having words of n-bit length in response to measured analog signal voltages, each bit column of the code having an assigned value y 1,2,3 . . . n in descending order in accordance with the number of level transitions in the bit column, each bit column having 2n y transitions and 2y spaces between transitions the combination comprising a. means for simultaneously comparing said signal with reference voltages at z 2n-1 discrete voltage levels, b. means for generating a signal having a first polarity representative of 1 at each reference level at which said signal exceeds said reference voltage and having a second polarity representative of 0 at each reference level at which said reference level exceeds said signal, c. means for generating the complement of said signal at each reference level, d. means for connecting said first and second polarity signals and said first and second polarity signal complements according to the relationship:

Claim 39

Apparatus for generating a digital code having two levels and having words of n-bit length in response to measured analog signal voltages, each bit column of the code having an assigned value y 1,2,3 . . . n in descending order in accordance with the number of level transitions in the bit column, each bit column having 2n y transitions and 2y spaces between transitions the combination comprising a. means for simultaneously comparing said signal with reference voltages at z 2n-1 discrete voltage levels, b. means for generating a signal having a first polarity representative of 1 at each reference level at which said signal exceeds said reference voltage and having a second polarity representative of 0 at each reference level at which said reference level exceeds said signal, c. means for generating the complement of said signal at each reference level, d. means for connecting said first and second polarity signals and said first and second polarity signal complements according to the relationship:

Claim 40

Apparatus for converting An analog signal waveform to digital form and for storing said digital signal in a memory during a record mode of operation and for reading out said digital signal from said memory during a playback mode of operation comprising: a. triggering means receiving said analog signal for generating a trigger pulse at predetermined point on the waveform of said signal; b. means for providing an adjustable rate clock signal; c. analog-to-digital converter means receiving said analog signal for converting said signal to digital code words of x-bit length; d. memory means for storing w digital code words of n-bit length in a recirculating format said memory having 1 through w discrete word addresses, at least one of said addresses being available for reading in or reading out a code word at a particular time; e. memory tracking counter means for indicating the address of the code word available at said memory means; f. interlace index counter means for indicating the memory means address at which the next code word is to be read-in or read-out; g. means for comparing addresses of said memory tracking counter means and said interlace index counter means for generating a coincidence pulse upon coincidence of said addresses; and h. control logic means receiving said clock pulses, said trigger pulses, and said coincidence pulses for providing read-in and read-out pulses.

Claim 41

Apparatus for converting An analog signal waveform to digital form and for storing said digital signal in a memory during a record mode of operation and for reading out said digital signal from said memory during a playback mode of operation comprising: a. triggering means receiving said analog signal for generating a trigger pulse at predetermined point on the waveform of said signal; b. means for providing an adjustable rate clock signal; c. analog-to-digital converter means receiving said analog signal for converting said signal to digital code words of x-bit length; d. memory means for storing w digital code words of n-bit length in a recirculating format said memory having 1 through w discrete word addresses, at least one of said addresses being available for reading in or reading out a code word at a particular time; e. memory tracking counter means for indicating the address of the code word available at said memory means; f. interlace index counter means for indicating the memory means address at which the next code word is to be read-in or read-out; g. means for comparing addresses of said memory tracking counter means and said interlace index counter means for generating a coincidence pulse upon coincidence of said addresses; and h. control logic means receiving said clock pulses, said trigger pulses, and said coincidence pulses for providing read-in and read-out pulses.

Claim 42

Apparatus according to claim 17 further comprising input buffer register means receiving said digital code words from said converter means and said read-in pulses for reading in a code word to said memory means upon receipt of a read-in pulse.

Claim 43

Apparatus according to claim 18 further comprising output buffer register means for reading out a code word from said memory upon receipt of a read-out pulse.