C-mos differential sense amplifier

Claim 1

A C-MOS differential sense amplifier for detecting voltage differences between the signals applied to its inputs (I,IN) in correspondence with a level transition of a clock signal (CKD), comprising: a level converter (LS) which receives at respective input terminals (I,IN) forming said inputs signals to be sensed for lowering a common mode voltage of said signals without attenuating voltage difference thereof, under control of clock signals (CKD, CKN); a sense circuit (DD), which receives at respective first (C) and second (CN) input terminals, signals supplied by said level converter (LS) and which transfers to a first (O) and to a second (ON) output a voltage difference present at the first and second input terminals enormously amplified by a high positive feedback under the control of clock signals (CKD, CKR); and a feedback block (FB) which receives at input terminals thereof the signals at the first and second outputs (O,ON) of said sense circuit (DD) and generates a feedback signal (RE) said level converter, said sense circuit and said feedback block being configured so that in a first inactive phase of a clock signal (CKD), the level converter (LS), the sense circuit (DD) and the feedback block (FB) are inactive and in a second active phase of a clock signal (CKD), immediately after a clock signal transition the differential sense amplifier reaches an operating point necessary to render the level converter (LS) and the sense circuit (DD) active to start the high positive feedback which switches the sense circuit (DD) and, finally, after the level transition of a delayed clock signal (CKR), the feedback signal (RE) generated by the feedback block (FB) reduces to zero a dissipation of the whole differential sense amplifier.